1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31#ifndef __DEV_NET_SINICREG_HH__
32#define __DEV_NET_SINICREG_HH__
33
34#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL);
35#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL);
36
37#define __SINIC_VAL32(NAME, OFFSET, WIDTH) \
38        static const uint32_t NAME##_width = WIDTH; \
39        static const uint32_t NAME##_offset = OFFSET; \
40        static const uint32_t NAME##_mask = (1 << WIDTH) - 1; \
41        static const uint32_t NAME = ((1 << WIDTH) - 1) << OFFSET; \
42        static inline uint32_t get_##NAME(uint32_t reg) \
43        { return (reg & NAME) >> OFFSET; } \
44        static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \
45        { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
46
47#define __SINIC_VAL64(NAME, OFFSET, WIDTH) \
48        static const uint64_t NAME##_width = WIDTH; \
49        static const uint64_t NAME##_offset = OFFSET; \
50        static const uint64_t NAME##_mask = (ULL(1) << WIDTH) - 1; \
51        static const uint64_t NAME = ((ULL(1) << WIDTH) - 1) << OFFSET; \
52        static inline uint64_t get_##NAME(uint64_t reg) \
53        { return (reg & NAME) >> OFFSET; } \
54        static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
55        { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
56
57namespace Sinic {
58namespace Regs {
59
60static const int VirtualShift = 8;
61static const int VirtualMask = 0xff;
62
63// Registers
64__SINIC_REG32(Config,        0x00) // 32: configuration register
65__SINIC_REG32(Command,       0x04) // 32: command register
66__SINIC_REG32(IntrStatus,    0x08) // 32: interrupt status
67__SINIC_REG32(IntrMask,      0x0c) // 32: interrupt mask
68__SINIC_REG32(RxMaxCopy,     0x10) // 32: max bytes per rx copy
69__SINIC_REG32(TxMaxCopy,     0x14) // 32: max bytes per tx copy
70__SINIC_REG32(ZeroCopySize,  0x18) // 32: bytes to copy if below threshold
71__SINIC_REG32(ZeroCopyMark,  0x1c) // 32: only zero-copy above this threshold
72__SINIC_REG32(VirtualCount,  0x20) // 32: number of virutal NICs
73__SINIC_REG32(RxMaxIntr,     0x24) // 32: max receives per interrupt
74__SINIC_REG32(RxFifoSize,    0x28) // 32: rx fifo capacity in bytes
75__SINIC_REG32(TxFifoSize,    0x2c) // 32: tx fifo capacity in bytes
76__SINIC_REG32(RxFifoLow,     0x30) // 32: rx fifo low watermark
77__SINIC_REG32(TxFifoLow,     0x34) // 32: tx fifo low watermark
78__SINIC_REG32(RxFifoHigh,    0x38) // 32: rx fifo high watermark
79__SINIC_REG32(TxFifoHigh,    0x3c) // 32: tx fifo high watermark
80__SINIC_REG32(RxData,        0x40) // 64: receive data
81__SINIC_REG32(RxDone,        0x48) // 64: receive done
82__SINIC_REG32(RxWait,        0x50) // 64: receive done (busy wait)
83__SINIC_REG32(TxData,        0x58) // 64: transmit data
84__SINIC_REG32(TxDone,        0x60) // 64: transmit done
85__SINIC_REG32(TxWait,        0x68) // 64: transmit done (busy wait)
86__SINIC_REG32(HwAddr,        0x70) // 64: mac address
87__SINIC_REG32(RxStatus,      0x78)
88__SINIC_REG32(Size,          0x80) // register addres space size
89
90// Config register bits
91__SINIC_VAL32(Config_ZeroCopy, 12, 1) // enable zero copy
92__SINIC_VAL32(Config_DelayCopy,11, 1) // enable delayed copy
93__SINIC_VAL32(Config_RSS,      10, 1) // enable receive side scaling
94__SINIC_VAL32(Config_RxThread,  9, 1) // enable receive threads
95__SINIC_VAL32(Config_TxThread,  8, 1) // enable transmit thread
96__SINIC_VAL32(Config_Filter,    7, 1) // enable receive filter
97__SINIC_VAL32(Config_Vlan,      6, 1) // enable vlan tagging
98__SINIC_VAL32(Config_Vaddr,     5, 1) // enable virtual addressing
99__SINIC_VAL32(Config_Desc,      4, 1) // enable tx/rx descriptors
100__SINIC_VAL32(Config_Poll,      3, 1) // enable polling
101__SINIC_VAL32(Config_IntEn,     2, 1) // enable interrupts
102__SINIC_VAL32(Config_TxEn,      1, 1) // enable transmit
103__SINIC_VAL32(Config_RxEn,      0, 1) // enable receive
104
105// Command register bits
106__SINIC_VAL32(Command_Intr,  1, 1) // software interrupt
107__SINIC_VAL32(Command_Reset, 0, 1) // reset chip
108
109// Interrupt register bits
110__SINIC_VAL32(Intr_Soft,      8, 1) // software interrupt
111__SINIC_VAL32(Intr_TxLow,     7, 1) // tx fifo dropped below watermark
112__SINIC_VAL32(Intr_TxFull,    6, 1) // tx fifo full
113__SINIC_VAL32(Intr_TxDMA,     5, 1) // tx dma completed w/ interrupt
114__SINIC_VAL32(Intr_TxPacket,  4, 1) // packet transmitted
115__SINIC_VAL32(Intr_RxHigh,    3, 1) // rx fifo above high watermark
116__SINIC_VAL32(Intr_RxEmpty,   2, 1) // rx fifo empty
117__SINIC_VAL32(Intr_RxDMA,     1, 1) // rx dma completed w/ interrupt
118__SINIC_VAL32(Intr_RxPacket,  0, 1) // packet received
119__SINIC_REG32(Intr_All,       0x01ff) // all valid interrupts
120__SINIC_REG32(Intr_NoDelay,   0x01cc) // interrupts that aren't coalesced
121__SINIC_REG32(Intr_Res,      ~0x01ff) // reserved interrupt bits
122
123// RX Data Description
124__SINIC_VAL64(RxData_NoDelay,  61,  1) // Don't Delay this copy
125__SINIC_VAL64(RxData_Vaddr,    60,  1) // Addr is virtual
126__SINIC_VAL64(RxData_Len,      40, 20) // 0 - 256k
127__SINIC_VAL64(RxData_Addr,      0, 40) // Address 1TB
128
129// TX Data Description
130__SINIC_VAL64(TxData_More,     63,  1) // Packet not complete (will dma more)
131__SINIC_VAL64(TxData_Checksum, 62,  1) // do checksum
132__SINIC_VAL64(TxData_Vaddr,    60,  1) // Addr is virtual
133__SINIC_VAL64(TxData_Len,      40, 20) // 0 - 256k
134__SINIC_VAL64(TxData_Addr,      0, 40) // Address 1TB
135
136// RX Done/Busy Information
137__SINIC_VAL64(RxDone_Packets,   32, 16) // number of packets in rx fifo
138__SINIC_VAL64(RxDone_Busy,      31,  1) // receive dma busy copying
139__SINIC_VAL64(RxDone_Complete,  30,  1) // valid data (packet complete)
140__SINIC_VAL64(RxDone_More,      29,  1) // Packet has more data (dma again)
141__SINIC_VAL64(RxDone_Empty,     28,  1) // rx fifo is empty
142__SINIC_VAL64(RxDone_High,      27,  1) // rx fifo is above the watermark
143__SINIC_VAL64(RxDone_NotHigh,   26,  1) // rxfifo never hit the high watermark
144__SINIC_VAL64(RxDone_TcpError,  25,  1) // TCP packet error (bad checksum)
145__SINIC_VAL64(RxDone_UdpError,  24,  1) // UDP packet error (bad checksum)
146__SINIC_VAL64(RxDone_IpError,   23,  1) // IP packet error (bad checksum)
147__SINIC_VAL64(RxDone_TcpPacket, 22,  1) // this is a TCP packet
148__SINIC_VAL64(RxDone_UdpPacket, 21,  1) // this is a UDP packet
149__SINIC_VAL64(RxDone_IpPacket,  20,  1) // this is an IP packet
150__SINIC_VAL64(RxDone_CopyLen,    0, 20) // up to 256k
151
152// TX Done/Busy Information
153__SINIC_VAL64(TxDone_Packets,   32, 16) // number of packets in tx fifo
154__SINIC_VAL64(TxDone_Busy,      31,  1) // transmit dma busy copying
155__SINIC_VAL64(TxDone_Complete,  30,  1) // valid data (packet complete)
156__SINIC_VAL64(TxDone_Full,      29,  1) // tx fifo is full
157__SINIC_VAL64(TxDone_Low,       28,  1) // tx fifo is below the watermark
158__SINIC_VAL64(TxDone_Res0,      27,  1) // reserved
159__SINIC_VAL64(TxDone_Res1,      26,  1) // reserved
160__SINIC_VAL64(TxDone_Res2,      25,  1) // reserved
161__SINIC_VAL64(TxDone_Res3,      24,  1) // reserved
162__SINIC_VAL64(TxDone_Res4,      23,  1) // reserved
163__SINIC_VAL64(TxDone_Res5,      22,  1) // reserved
164__SINIC_VAL64(TxDone_Res6,      21,  1) // reserved
165__SINIC_VAL64(TxDone_Res7,      20,  1) // reserved
166__SINIC_VAL64(TxDone_CopyLen,    0, 20) // up to 256k
167
168__SINIC_VAL64(RxStatus_Dirty,   48, 16)
169__SINIC_VAL64(RxStatus_Mapped,  32, 16)
170__SINIC_VAL64(RxStatus_Busy,    16, 16)
171__SINIC_VAL64(RxStatus_Head,     0, 16)
172
173struct Info
174{
175    uint8_t size;
176    bool read;
177    bool write;
178    const char *name;
179};
180
181} // namespace Regs
182
183inline const Regs::Info&
184regInfo(Addr daddr)
185{
186    static Regs::Info invalid = { 0, false, false, "invalid" };
187    static Regs::Info info [] = {
188        { 4, true,  true,  "Config"       },
189        { 4, false, true,  "Command"      },
190        { 4, true,  true,  "IntrStatus"   },
191        { 4, true,  true,  "IntrMask"     },
192        { 4, true,  false, "RxMaxCopy"    },
193        { 4, true,  false, "TxMaxCopy"    },
194        { 4, true,  false, "ZeroCopySize" },
195        { 4, true,  false, "ZeroCopyMark" },
196        { 4, true,  false, "VirtualCount" },
197        { 4, true,  false, "RxMaxIntr"    },
198        { 4, true,  false, "RxFifoSize"   },
199        { 4, true,  false, "TxFifoSize"   },
200        { 4, true,  false, "RxFifoLow"    },
201        { 4, true,  false, "TxFifoLow"    },
202        { 4, true,  false, "RxFifoHigh"   },
203        { 4, true,  false, "TxFifoHigh"   },
204        { 8, true,  true,  "RxData"       },
205        invalid,
206        { 8, true,  false, "RxDone"       },
207        invalid,
208        { 8, true,  false, "RxWait"       },
209        invalid,
210        { 8, true,  true,  "TxData"       },
211        invalid,
212        { 8, true,  false, "TxDone"       },
213        invalid,
214        { 8, true,  false, "TxWait"       },
215        invalid,
216        { 8, true,  false, "HwAddr"       },
217        invalid,
218        { 8, true,  false, "RxStatus"     },
219        invalid,
220    };
221
222    return info[daddr / 4];
223}
224
225inline bool
226regValid(Addr daddr)
227{
228    if (daddr > Regs::Size)
229        return false;
230
231    if (regInfo(daddr).size == 0)
232        return false;
233
234    return true;
235}
236
237} // namespace Sinic
238
239#endif // __DEV_NET_SINICREG_HH__
240