1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Ali Saidi
31 *          Korey Sewell
32 *          Alec Roelke
33 */
34#include "arch/riscv/process.hh"
35
36#include <algorithm>
37#include <cstddef>
38#include <iostream>
39#include <iterator>
40#include <map>
41#include <string>
42#include <vector>
43
44#include "arch/riscv/isa.hh"
45#include "arch/riscv/isa_traits.hh"
46#include "arch/riscv/registers.hh"
47#include "base/loader/elf_object.hh"
48#include "base/loader/object_file.hh"
49#include "base/logging.hh"
50#include "base/random.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Stack.hh"
53#include "mem/page_table.hh"
54#include "params/Process.hh"
55#include "sim/aux_vector.hh"
56#include "sim/process.hh"
57#include "sim/process_impl.hh"
58#include "sim/syscall_return.hh"
59#include "sim/system.hh"
60
61using namespace std;
62using namespace RiscvISA;
63
64RiscvProcess::RiscvProcess(ProcessParams *params, ObjectFile *objFile) :
65        Process(params,
66                new EmulationPageTable(params->name, params->pid, PageBytes),
67                objFile)
68{
69    fatal_if(params->useArchPT, "Arch page tables not implemented.");
70}
71
72RiscvProcess64::RiscvProcess64(ProcessParams *params, ObjectFile *objFile) :
73        RiscvProcess(params, objFile)
74{
75    const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
76    const Addr max_stack_size = 8 * 1024 * 1024;
77    const Addr next_thread_stack_base = stack_base - max_stack_size;
78    const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
79            PageBytes);
80    const Addr mmap_end = 0x4000000000000000L;
81    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
82            next_thread_stack_base, mmap_end);
83}
84
85RiscvProcess32::RiscvProcess32(ProcessParams *params, ObjectFile *objFile) :
86        RiscvProcess(params, objFile)
87{
88    const Addr stack_base = 0x7FFFFFFF;
89    const Addr max_stack_size = 8 * 1024 * 1024;
90    const Addr next_thread_stack_base = stack_base - max_stack_size;
91    const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
92            PageBytes);
93    const Addr mmap_end = 0x40000000L;
94    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
95                                     next_thread_stack_base, mmap_end);
96}
97
98void
99RiscvProcess64::initState()
100{
101    Process::initState();
102
103    argsInit<uint64_t>(PageBytes);
104    for (ContextID ctx: contextIds)
105        system->getThreadContext(ctx)->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
106}
107
108void
109RiscvProcess32::initState()
110{
111    Process::initState();
112
113    argsInit<uint32_t>(PageBytes);
114    for (ContextID ctx: contextIds) {
115        system->getThreadContext(ctx)->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
116        PCState pc = system->getThreadContext(ctx)->pcState();
117        pc.rv32(true);
118        system->getThreadContext(ctx)->pcState(pc);
119    }
120}
121
122template<class IntType> void
123RiscvProcess::argsInit(int pageSize)
124{
125    const int RandomBytes = 16;
126    const int addrSize = sizeof(IntType);
127
128    updateBias();
129    objFile->loadSections(initVirtMem);
130    ElfObject* elfObject = dynamic_cast<ElfObject*>(objFile);
131    memState->setStackMin(memState->getStackBase());
132
133    // Determine stack size and populate auxv
134    Addr stack_top = memState->getStackMin();
135    stack_top -= RandomBytes;
136    for (const string& arg: argv)
137        stack_top -= arg.size() + 1;
138    for (const string& env: envp)
139        stack_top -= env.size() + 1;
140    stack_top &= -addrSize;
141
142    vector<AuxVector<IntType>> auxv;
143    if (elfObject != nullptr) {
144        auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
145        auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
146        auxv.emplace_back(M5_AT_PHENT, elfObject->programHeaderSize());
147        auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
148        auxv.emplace_back(M5_AT_PAGESZ, PageBytes);
149        auxv.emplace_back(M5_AT_SECURE, 0);
150        auxv.emplace_back(M5_AT_RANDOM, stack_top);
151        auxv.emplace_back(M5_AT_NULL, 0);
152    }
153    stack_top -= (1 + argv.size()) * addrSize +
154                   (1 + envp.size()) * addrSize +
155                   addrSize + 2 * sizeof(IntType) * auxv.size();
156    stack_top &= -2*addrSize;
157    memState->setStackSize(memState->getStackBase() - stack_top);
158    allocateMem(roundDown(stack_top, pageSize),
159            roundUp(memState->getStackSize(), pageSize));
160
161    // Copy random bytes (for AT_RANDOM) to stack
162    memState->setStackMin(memState->getStackMin() - RandomBytes);
163    uint8_t at_random[RandomBytes];
164    generate(begin(at_random), end(at_random),
165             [&]{ return random_mt.random(0, 0xFF); });
166    initVirtMem.writeBlob(memState->getStackMin(), at_random, RandomBytes);
167
168    // Copy argv to stack
169    vector<Addr> argPointers;
170    for (const string& arg: argv) {
171        memState->setStackMin(memState->getStackMin() - (arg.size() + 1));
172        initVirtMem.writeString(memState->getStackMin(), arg.c_str());
173        argPointers.push_back(memState->getStackMin());
174        if (DTRACE(Stack)) {
175            string wrote;
176            initVirtMem.readString(wrote, argPointers.back());
177            DPRINTFN("Wrote arg \"%s\" to address %p\n",
178                    wrote, (void*)memState->getStackMin());
179        }
180    }
181    argPointers.push_back(0);
182
183    // Copy envp to stack
184    vector<Addr> envPointers;
185    for (const string& env: envp) {
186        memState->setStackMin(memState->getStackMin() - (env.size() + 1));
187        initVirtMem.writeString(memState->getStackMin(), env.c_str());
188        envPointers.push_back(memState->getStackMin());
189        DPRINTF(Stack, "Wrote env \"%s\" to address %p\n",
190                env, (void*)memState->getStackMin());
191    }
192    envPointers.push_back(0);
193
194    // Align stack
195    memState->setStackMin(memState->getStackMin() & -addrSize);
196
197    // Calculate bottom of stack
198    memState->setStackMin(memState->getStackMin() -
199            ((1 + argv.size()) * addrSize +
200             (1 + envp.size()) * addrSize +
201             addrSize + 2 * sizeof(IntType) * auxv.size()));
202    memState->setStackMin(memState->getStackMin() & (-2 * addrSize));
203    Addr sp = memState->getStackMin();
204    const auto pushOntoStack =
205        [this, &sp](IntType data) {
206            initVirtMem.write(sp, data, GuestByteOrder);
207            sp += sizeof(data);
208        };
209
210    // Push argc and argv pointers onto stack
211    IntType argc = argv.size();
212    DPRINTF(Stack, "Wrote argc %d to address %#x\n", argc, sp);
213    pushOntoStack(argc);
214
215    for (const Addr& argPointer: argPointers) {
216        DPRINTF(Stack, "Wrote argv pointer %#x to address %#x\n",
217                argPointer, sp);
218        pushOntoStack(argPointer);
219    }
220
221    // Push env pointers onto stack
222    for (const Addr& envPointer: envPointers) {
223        DPRINTF(Stack, "Wrote envp pointer %#x to address %#x\n",
224                envPointer, sp);
225        pushOntoStack(envPointer);
226    }
227
228    // Push aux vector onto stack
229    std::map<IntType, string> aux_keys = {
230        {M5_AT_ENTRY, "M5_AT_ENTRY"},
231        {M5_AT_PHNUM, "M5_AT_PHNUM"},
232        {M5_AT_PHENT, "M5_AT_PHENT"},
233        {M5_AT_PHDR, "M5_AT_PHDR"},
234        {M5_AT_PAGESZ, "M5_AT_PAGESZ"},
235        {M5_AT_SECURE, "M5_AT_SECURE"},
236        {M5_AT_RANDOM, "M5_AT_RANDOM"},
237        {M5_AT_NULL, "M5_AT_NULL"}
238    };
239    for (const auto &aux: auxv) {
240        DPRINTF(Stack, "Wrote aux key %s to address %#x\n",
241                aux_keys[aux.type], sp);
242        pushOntoStack(aux.type);
243        DPRINTF(Stack, "Wrote aux value %x to address %#x\n", aux.val, sp);
244        pushOntoStack(aux.val);
245    }
246
247    ThreadContext *tc = system->getThreadContext(contextIds[0]);
248    tc->setIntReg(StackPointerReg, memState->getStackMin());
249    tc->pcState(getStartPC());
250
251    memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
252}
253
254RegVal
255RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
256{
257    // If a larger index is requested than there are syscall argument
258    // registers, return 0
259    RegVal retval = 0;
260    if (i < SyscallArgumentRegs.size())
261        retval = tc->readIntReg(SyscallArgumentRegs[i]);
262    i++;
263    return retval;
264}
265
266void
267RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
268{
269    tc->setIntReg(SyscallArgumentRegs[i], val);
270}
271
272void
273RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
274{
275    if (sysret.successful()) {
276        // no error
277        tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue());
278    } else {
279        // got an error, return details
280        tc->setIntReg(SyscallPseudoReturnReg, sysret.encodedValue());
281    }
282}
283