Searched refs:tc (Results 151 - 175 of 304) sorted by relevance

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/gem5/src/arch/x86/
H A Disa.cc46 ThreadContext *tc)
101 if (tc)
102 tc->getDecoderPtr()->setM5Reg(m5reg);
139 ISA::readMiscReg(int miscReg, ThreadContext * tc) argument
142 return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
197 ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) argument
219 dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
220 dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
230 tc);
236 dynamic_cast<TLB *>(tc
44 updateHandyM5Reg(Efer efer, CR0 cr0, SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags, ThreadContext *tc) argument
416 startup(ThreadContext *tc) argument
[all...]
H A Dtlb.cc173 TLB::translateInt(const RequestPtr &req, ThreadContext *tc) argument
207 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
228 ThreadContext *tc, Mode mode) const
242 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
260 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
270 ThreadContext *tc, Translation *translation,
282 return translateInt(req, tc);
288 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
299 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
302 SegAttr attr = tc
227 finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const argument
269 translate(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing) argument
430 translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) argument
437 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) argument
[all...]
/gem5/src/arch/riscv/
H A Dfaults.hh111 virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
112 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
124 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
155 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
168 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
182 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
196 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
223 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
248 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
H A Dremote_gdb.cc151 RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc, int _port) argument
152 : BaseRemoteGDB(_system, tc, _port), regCache(this)
/gem5/src/arch/sparc/
H A Disa.hh119 void setFSReg(int miscReg, RegVal val, ThreadContext *tc);
120 RegVal readFSReg(int miscReg, ThreadContext * tc);
123 void checkSoftInt(ThreadContext *tc);
127 void processTickCompare(ThreadContext *tc);
128 void processSTickCompare(ThreadContext *tc);
129 void processHSTickCompare(ThreadContext *tc);
174 void startup(ThreadContext *tc) {} argument
187 RegVal readMiscReg(int miscReg, ThreadContext *tc);
190 void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
H A Dinterrupts.hh134 checkInterrupts(ThreadContext *tc) const
139 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
140 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
192 getInterrupt(ThreadContext *tc) argument
194 assert(checkInterrupts(tc));
196 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
197 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
249 updateIntrInfo(ThreadContext *tc) argument
H A Dtlb.hh154 Fault translateInst(const RequestPtr &req, ThreadContext *tc);
155 Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
172 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
174 const RequestPtr &req, ThreadContext *tc,
178 ThreadContext *tc, Mode mode) const override;
179 Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
180 Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
181 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
/gem5/src/arch/mips/
H A Dstacktrace.cc46 ProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc)
58 PortProxy &vp = tc->getVirtProxy();
73 PortProxy &vp = tc->getVirtProxy();
87 tc->getVirtProxy().readString(comm, task + name_off, sizeof(comm));
95 : tc(0), stack(64)
100 : tc(0), stack(64)
112 tc = _tc;
205 MachInst inst = tc->getVirtProxy().read<MachInst>(pc);
215 ra = tc->getVirtProxy().read<Addr>(sp + disp);
H A Dprocess.cc191 ThreadContext *tc = system->getThreadContext(contextIds[0]); local
193 setSyscallArg(tc, 0, argc);
194 setSyscallArg(tc, 1, argv_array_base);
195 tc->setIntReg(StackPointerReg, memState->getStackMin());
197 tc->pcState(getStartPC());
202 MipsProcess::getSyscallArg(ThreadContext *tc, int &i) argument
205 return tc->readIntReg(FirstArgumentReg + i++);
209 MipsProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val) argument
212 tc->setIntReg(FirstArgumentReg + i, val);
216 MipsProcess::setSyscallReturn(ThreadContext *tc, SyscallRetur argument
[all...]
H A Dutility.cc51 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) argument
232 startupCPU(ThreadContext *tc, int cpuId) argument
234 tc->activate();
238 initCPU(ThreadContext *tc, int cpuId) argument
269 skipFunction(ThreadContext *tc) argument
271 PCState newPC = tc->pcState();
272 newPC.set(tc->readIntReg(ReturnAddressReg));
273 tc->pcState(newPC);
/gem5/src/arch/arm/
H A Dnativetrace.cc102 Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) argument
110 newState[i] = tc->readIntReg(i);
115 newState[STATE_PC] = tc->pcState().npc();
119 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
120 cpsr.nz = tc->readCCReg(CCREG_NZ);
121 cpsr.c = tc->readCCReg(CCREG_C);
122 cpsr.v = tc->readCCReg(CCREG_V);
123 cpsr.ge = tc->readCCReg(CCREG_GE);
129 auto vec(tc->readVecReg(RegId(VecRegClass,i))
134 newState[STATE_FPSCR] = tc
141 ThreadContext *tc = record->getThread(); local
[all...]
H A Dsemihosting.cc156 ArmSemihosting::call64(ThreadContext *tc, uint32_t op, uint64_t param) argument
173 PortProxy &proxy = physProxy(tc);
174 ByteOrder endian = ArmISA::byteOrder(tc);
183 auto ret_errno = (this->*call->call)(tc, true, argv);
191 ArmSemihosting::call32(ThreadContext *tc, uint32_t op, uint32_t param) argument
208 PortProxy &proxy = physProxy(tc);
209 ByteOrder endian = ArmISA::byteOrder(tc);
218 auto ret_errno = (this->*call->call)(tc, false, argv);
253 ArmSemihosting::physProxy(ThreadContext *tc) argument
255 if (ArmISA::inSecureState(tc)) {
270 readString(ThreadContext *tc, Addr ptr, size_t len) argument
281 callOpen(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
309 callClose(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
332 callWriteC(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
344 callWrite0(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
361 callWrite(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
382 callRead(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
403 callReadC(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
410 callIsError(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
421 callIsTTY(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
436 callSeek(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
451 callFLen(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
466 callTmpNam(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
487 callRemove(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
500 callRename(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
514 callClock(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
521 callTime(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
528 callSystem(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
539 callErrno(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
547 callGetCmdLine(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
566 callHeapInfo(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
624 callExit(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
637 callExitExtended(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
658 callElapsed(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
677 callTickFreq(ThreadContext *tc, bool aarch64, std::vector<uint64_t> &argv) argument
[all...]
H A Dstage2_lookup.cc57 Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe) argument
60 fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this, timing,
69 if (ELIs64(tc, EL2))
70 fault = stage2Tlb->checkPermissions64(stage2Te, req, mode, tc);
180 ThreadContext *tc, BaseTLB::Mode mode)
185 fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this,
195 transState->finish(fault, s1Req, tc, mode);
199 stage1Tlb->translateComplete(s1Req, tc, transState, mode, tranType, true);
179 finish(const Fault &_fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) argument
H A Dtlb.cc118 TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) argument
120 updateMiscReg(tc);
124 return stage2Tlb->translateFunctional(tc, va, pa);
137 ThreadContext *tc, Mode mode) const
565 TLB::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, argument
568 updateMiscReg(tc);
572 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
595 Process *p = tc->getProcessPtr();
601 return finalizePhysical(req, tc, mode);
784 ThreadContext *tc)
136 finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const argument
783 checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc) argument
1016 checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode) argument
1036 translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, TLB::ArmTranslationType tranType, bool functional) argument
1200 translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, TLB::ArmTranslationType tranType) argument
1221 translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode, TLB::ArmTranslationType tranType) argument
1242 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, TLB::ArmTranslationType tranType) argument
1259 translateComplete(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, TLB::ArmTranslationType tranType, bool callFromS2) argument
1293 updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) argument
1452 getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, TLB::ArmTranslationType tranType) argument
1519 getResultTe(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, TlbEntry *mergeTe) argument
[all...]
H A Disa_device.hh67 virtual void setThreadContext(ThreadContext *tc) {} argument
/gem5/src/base/
H A Dcp_annotate.hh87 void swSmBegin(ThreadContext *tc) { return; } argument
88 void swSmEnd(ThreadContext *tc) { return; } argument
89 void swExplictBegin(ThreadContext *tc) { return; } argument
90 void swAutoBegin(ThreadContext *tc, Addr next_pc) { return; } argument
91 void swEnd(ThreadContext *tc) { return; } argument
92 void swQ(ThreadContext *tc) { return; } argument
93 void swDq(ThreadContext *tc) { return; } argument
94 void swPq(ThreadContext *tc) { return; } argument
95 void swRq(ThreadContext *tc) { return; } argument
96 void swWf(ThreadContext *tc) { retur argument
97 swWe(ThreadContext *tc) argument
98 swSq(ThreadContext *tc) argument
99 swAq(ThreadContext *tc) argument
100 swLink(ThreadContext *tc) argument
101 swIdentify(ThreadContext *tc) argument
102 swGetId(ThreadContext *tc) argument
103 swSyscallLink(ThreadContext *tc) argument
[all...]
/gem5/src/cpu/
H A Dpc_event.hh63 virtual void process(ThreadContext *tc) = 0;
95 bool doService(ThreadContext *tc);
103 bool service(ThreadContext *tc) argument
108 return doService(tc);
142 virtual void process(ThreadContext *tc);
153 virtual void process(ThreadContext *tc);
H A Dexetrace.hh71 getInstRecord(Tick when, ThreadContext *tc, argument
78 return new ExeTracerRecord(when, tc,
/gem5/src/gpu-compute/
H A Dcl_driver.cc96 ClDriver::open(ThreadContext *tc, int mode, int flags) argument
98 auto p = tc->getProcessPtr();
106 ClDriver::ioctl(ThreadContext *tc, unsigned req) argument
109 auto process = tc->getProcessPtr();
110 Addr buf_addr = process->getSyscallArg(tc, index);
140 sizes.copyOut(tc->getVirtProxy());
161 kinfo.copyOut(tc->getVirtProxy());
186 buf.copyOut(tc->getVirtProxy());
201 data.copyOut(tc->getVirtProxy());
230 buf.copyOut(tc
[all...]
/gem5/src/arch/arm/insts/
H A Dstatic_inst.hh204 uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)
207 bool haveVirt = ArmSystem::haveVirtualization(tc);
208 bool haveSecurity = ArmSystem::haveSecurity(tc);
236 if (!badMode(tc, newMode)) {
373 bool isWFxTrapping(ThreadContext *tc,
402 Fault checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const;
411 Fault checkFPAdvSIMDEnabled64(ThreadContext *tc,
420 Fault checkAdvSIMDOrFPEnabled32(ThreadContext *tc,
431 Fault checkForWFxTrap32(ThreadContext *tc,
440 Fault checkForWFxTrap64(ThreadContext *tc,
203 cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc) argument
547 getCurSveVecLenInQWords(ThreadContext *tc) argument
554 getCurSveVecLen(ThreadContext *tc) argument
[all...]
/gem5/src/sim/
H A Dsyscall_desc.hh59 ThreadContext *tc);
99 * @param tc Handle for owning ThreadContext to pass information
101 void doSyscall(int callnum, ThreadContext *tc, Fault *fault);
/gem5/src/arch/alpha/
H A Disa.cc98 ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
112 return readIpr(misc_reg, tc);
143 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
162 setIpr(misc_reg, val, tc);
/gem5/src/mem/
H A Dfs_translating_port_proxy.hh80 FSTranslatingPortProxy(ThreadContext* tc);
H A Dfs_translating_port_proxy.cc57 FSTranslatingPortProxy::FSTranslatingPortProxy(ThreadContext *tc) argument
58 : PortProxy(tc->getCpuPtr()->getSendFunctional(),
59 tc->getSystemPtr()->cacheLineSize()), _tc(tc)
/gem5/src/arch/mips/linux/
H A Dsystem.hh59 virtual void process(ThreadContext *tc);
67 virtual void process(ThreadContext *tc);
95 void setDelayLoop(ThreadContext *tc);

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