1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 *          Andreas Hansson
42 */
43
44/**
45 * @file
46 * TranslatingPortProxy Object Declaration for FS.
47 *
48 * Port proxies are used when non structural entities need access to
49 * the memory system. Proxy objects replace the previous
50 * FunctionalPort, TranslatingPort and VirtualPort objects, which
51 * provided the same functionality as the proxies, but were instances
52 * of ports not corresponding to real structural ports of the
53 * simulated system. Via the port proxies all the accesses go through
54 * an actual port and thus are transparent to a potentially
55 * distributed memory and automatically adhere to the memory map of
56 * the system.
57 */
58
59#ifndef __MEM_FS_TRANSLATING_PORT_PROXY_HH__
60#define __MEM_FS_TRANSLATING_PORT_PROXY_HH__
61
62#include "mem/port_proxy.hh"
63
64class ThreadContext;
65
66/**
67 * A TranslatingPortProxy in FS mode translates a virtual address to a
68 * physical address and then calls the read/write functions of the
69 * port. If a thread context is provided the address can alway be
70 * translated, If not it can only be translated if it is a simple
71 * address masking operation (such as alpha super page accesses).
72 */
73class FSTranslatingPortProxy : public PortProxy
74{
75  private:
76    ThreadContext* _tc;
77
78  public:
79
80    FSTranslatingPortProxy(ThreadContext* tc);
81
82    FSTranslatingPortProxy(SendFunctionalFunc func,
83                           unsigned int cacheLineSize);
84    FSTranslatingPortProxy(MasterPort &port,
85                           unsigned int cacheLineSize);
86
87    ~FSTranslatingPortProxy() {}
88
89    /** Version of tryReadblob that translates virt->phys and deals
90      * with page boundries. */
91    bool tryReadBlob(Addr addr, void *p, int size) const override;
92
93    /** Version of tryWriteBlob that translates virt->phys and deals
94      * with page boundries. */
95    bool tryWriteBlob(Addr addr, const void *p, int size) const override;
96
97    /**
98     * Fill size bytes starting at addr with byte value val.
99     */
100    bool tryMemsetBlob(Addr address, uint8_t  v, int size) const override;
101};
102
103#endif //__MEM_FS_TRANSLATING_PORT_PROXY_HH__
104