arch/arm/tlb.cc

118 TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
120     updateMiscReg(tc);
124         return stage2Tlb->translateFunctional(tc, va, pa);
137                       ThreadContext *tc, Mode mode) const
565 TLB::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
568     updateMiscReg(tc);
572         vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
595     Process *p = tc->getProcessPtr();
601     return finalizePhysical(req, tc, mode);
784                         ThreadContext *tc)
798     Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
807     updateMiscReg(tc, curTranType);
867         assert(ArmSystem::haveVirtualization(tc) && aarch64EL != EL2);
917                 if (checkPAN(tc, ap, req, mode)) {
957             if (hcr.e2h && checkPAN(tc, ap, req, mode)) {
1016 TLB::checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode)
1025     AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
1036 TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
1043     updateMiscReg(tc, tranType);
1048         vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
1055     bool long_desc_format = aarch64 || longDescFormatInUse(tc);
1142     Fault fault = getResultTe(&te, req, tc, mode, translation, timing,
1193         return te ? finalizePhysical(req, tc, mode) : NoFault;
1200 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode,
1203     updateMiscReg(tc, tranType);
1207         return stage2Tlb->translateAtomic(req, tc, mode, tranType);
1213         fault = translateFs(req, tc, mode, NULL, delay, false, tranType);
1215         fault = translateSe(req, tc, mode, NULL, delay, false);
1221 TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode,
1224     updateMiscReg(tc, tranType);
1228         return stage2Tlb->translateFunctional(req, tc, mode, tranType);
1234         fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true);
1236         fault = translateSe(req, tc, mode, NULL, delay, false);
1242 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
1245     updateMiscReg(tc, tranType);
1249         stage2Tlb->translateTiming(req, tc, translation, mode, tranType);
1255     translateComplete(req, tc, translation, mode, tranType, isStage2);
1259 TLB::translateComplete(const RequestPtr &req, ThreadContext *tc,
1266         fault = translateFs(req, tc, mode, translation, delay, true, tranType);
1268         fault = translateSe(req, tc, mode, translation, delay, true);
1279             translation->finish(fault, req, tc, mode);
1293 TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
1298     if (miscRegValid && miscRegContext == tc->contextId() &&
1304     cpsr = tc->readMiscReg(MISCREG_CPSR);
1307     isSecure = inSecureState(tc) &&
1312         ELIs64(tc, EL2) :
1313         ELIs64(tc, aarch64EL == EL0 ? EL1 : aarch64EL);
1321                 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1322                 ttbcr = tc->readMiscReg(MISCREG_TCR_EL1);
1324                     tc->readMiscReg(MISCREG_TTBR1_EL1) :
1325                     tc->readMiscReg(MISCREG_TTBR0_EL1);
1331             sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2);
1332             ttbcr = tc->readMiscReg(MISCREG_TCR_EL2);
1336             sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3);
1337             ttbcr = tc->readMiscReg(MISCREG_TCR_EL3);
1341         hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1342         scr = tc->readMiscReg(MISCREG_SCR_EL3);
1345             vmid           = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
1368         sctlr  = tc->readMiscReg(snsBankedIndex(MISCREG_SCTLR, tc,
1370         ttbcr  = tc->readMiscReg(snsBankedIndex(MISCREG_TTBCR, tc,
1372         scr    = tc->readMiscReg(MISCREG_SCR);
1374         if (longDescFormatInUse(tc)) {
1375             uint64_t ttbr_asid = tc->readMiscReg(
1378                                        tc, !isSecure));
1381             CONTEXTIDR context_id = tc->readMiscReg(snsBankedIndex(
1382                 MISCREG_CONTEXTIDR, tc,!isSecure));
1385         prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR, tc,
1387         nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR, tc,
1389         dacr = tc->readMiscReg(snsBankedIndex(MISCREG_DACR, tc,
1391         hcr  = tc->readMiscReg(MISCREG_HCR);
1394             vmid   = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48);
1400                 sctlr = tc->readMiscReg(MISCREG_HSCTLR);
1418     miscRegContext = tc->contextId();
1452 TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
1459         updateMiscReg(tc, tranType);
1468         vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el, ttbcr);
1495         fault = tableWalker->walk(req, tc, asid, vmid, isHyp, mode,
1520         ThreadContext *tc, Mode mode,
1531         fault = getTE(&s2Te, req, tc, mode, translation, timing, functional,
1536                 fault = checkPermissions64(s2Te, req, mode, tc);
1549     fault = getTE(&s1Te, req, tc, mode, translation, timing, functional,
1555             fault = checkPermissions64(s1Te, req, mode, tc);
1561             fault = s2Lookup->getTe(tc, mergeTe);