Lines Matching refs:tc
46 ThreadContext *tc)
101 if (tc)
102 tc->getDecoderPtr()->setM5Reg(m5reg);
139 ISA::readMiscReg(int miscReg, ThreadContext * tc)
142 return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
197 ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
219 dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
220 dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
230 tc);
236 dynamic_cast<TLB *>(tc->getITBPtr())->flushNonGlobal();
237 dynamic_cast<TLB *>(tc->getDTBPtr())->flushNonGlobal();
243 dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
244 dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
272 tc);
281 tc);
309 regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
389 tc);
416 ISA::startup(ThreadContext *tc)
418 tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);