Lines Matching refs:tc
173 TLB::translateInt(const RequestPtr &req, ThreadContext *tc)
207 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
228 ThreadContext *tc, Mode mode) const
242 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
260 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
270 ThreadContext *tc, Translation *translation,
282 return translateInt(req, tc);
288 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
299 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
302 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
311 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
312 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
345 vaddr, tc->instAddr());
352 Fault fault = walker->start(tc, translation, req, mode);
361 Process *p = tc->getProcessPtr();
392 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
426 return finalizePhysical(req, tc, mode);
430 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
433 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
437 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
443 TLB::translate(req, tc, translation, mode, delayedResponse, true);
445 translation->finish(fault, req, tc, mode);