/gem5/src/cpu/pred/ |
H A D | 2bit_local.hh | 95 bool squashed, const StaticInstPtr & inst, Addr corrTarget);
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H A D | bi_mode.hh | 65 bool squashed, const StaticInstPtr & inst, Addr corrTarget);
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H A D | multiperspective_perceptron_tage_8KB.hh | 69 void scHistoryUpdate(Addr branch_pc, const StaticInstPtr &inst, bool taken,
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H A D | multiperspective_perceptron_tage_64KB.cc | 137 const StaticInstPtr &inst, bool taken, 140 int brtype = inst->isDirectCtrl() ? 0 : 2; 141 if (! inst->isUncondCtrl()) { 153 sh->updateHistoryStack(corrTarget, taken, inst->isCall(), 154 inst->isReturn()); 156 StatisticalCorrector::scHistoryUpdate(branch_pc, inst, taken, bi, 136 scHistoryUpdate(Addr branch_pc, const StaticInstPtr &inst, bool taken, StatisticalCorrector::BranchInfo *bi, Addr corrTarget) argument
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H A D | multiperspective_perceptron_tage.cc | 189 bool speculative, const StaticInstPtr &inst, Addr target) 199 int brtype = inst->isDirectCtrl() ? 0 : 2; 200 if (! inst->isUncondCtrl()) { 602 const StaticInstPtr & inst, 623 statisticalCorrector->scHistoryUpdate(instPC, inst, taken, 626 inst, corrTarget); 652 if (inst->isCondCtrl() && inst->isDirectCtrl() 653 && !inst->isCall() && !inst 187 updateHistories( ThreadID tid, Addr branch_pc, bool taken, TAGEBase::BranchInfo* b, bool speculative, const StaticInstPtr &inst, Addr target) argument 600 update(ThreadID tid, Addr instPC, bool taken, void *bp_history, bool squashed, const StaticInstPtr & inst, Addr corrTarget) argument [all...] |
H A D | tage.cc | 57 bool squashed, const StaticInstPtr & inst, Addr corrTarget) 83 tage->updateHistories(tid, branch_pc, taken, tage_bi, false, inst, 56 update(ThreadID tid, Addr branch_pc, bool taken, void* bp_history, bool squashed, const StaticInstPtr & inst, Addr corrTarget) argument
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H A D | ltage.cc | 95 bool squashed, const StaticInstPtr & inst, Addr corrTarget) 132 inst, corrTarget); 94 update(ThreadID tid, Addr branch_pc, bool taken, void* bp_history, bool squashed, const StaticInstPtr & inst, Addr corrTarget) argument
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H A D | 2bit_local.cc | 94 bool squashed, const StaticInstPtr & inst, Addr corrTarget) 93 update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history, bool squashed, const StaticInstPtr & inst, Addr corrTarget) argument
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H A D | tournament.hh | 104 * @param inst Static instruction information 109 bool squashed, const StaticInstPtr & inst, Addr corrTarget);
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H A D | multiperspective_perceptron_tage_64KB.hh | 72 void scHistoryUpdate(Addr branch_pc, const StaticInstPtr &inst, bool taken,
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/gem5/src/cpu/o3/ |
H A D | inst_queue_impl.hh | 67 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 75 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 76 inst = NULL; 323 .desc("FU busy rate (busy events/executed inst)") 628 // @todo: Clean up this code; can do it by setting inst as unable 629 // to issue, then calling normal insert on the inst. 685 DynInstPtr inst = std::move(instsToExecute.front()); local 687 if (inst->isFloating()) { 689 } else if (inst->isVector()) { 694 return inst; 752 processFUCompletion(const DynInstPtr &inst, int fu_idx) argument 944 scheduleNonSpec(const InstSeqNum &inst) argument 972 commit(const InstSeqNum &inst, ThreadID tid) argument 1452 addIfReady(const DynInstPtr &inst) argument [all...] |
H A D | commit_impl.hh | 647 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%llu]\n", 705 const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid); 709 tid, inst->seqNum, inst->pcState()); 712 const DynInstPtr &inst = rob->readHeadInst(tid); local 714 ppCommitStall->notify(inst); 718 tid, inst->seqNum, inst->pcState()); 1348 const DynInstPtr &inst = fromRename->insts[inst_num]; local 1349 ThreadID tid = inst 1395 updateComInstStats(const DynInstPtr &inst) argument [all...] |
H A D | lsq.hh | 90 DynInstPtr inst; member in class:LSQ::LSQSenderState 110 ContextID contextId() { return inst->contextId(); } 305 LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad) : argument 307 _port(*port), _inst(inst), _data(nullptr), 317 LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad, argument 325 _port(*port), _inst(inst), _data(data), 720 SingleDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad, argument 726 LSQRequest(port, inst, isLoad, addr, size, flags_, data, res, 779 SplitDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad, argument 784 LSQRequest(port, inst, isLoa [all...] |
H A D | rob_impl.hh | 206 ROB<Impl>::insertInst(const DynInstPtr &inst) argument 208 assert(inst); 212 DPRINTF(ROB, "Adding inst PC %s to the ROB.\n", inst->pcState()); 216 ThreadID tid = inst->threadNumber; 218 instList[tid].push_back(inst); 223 assert((*head) == inst); 227 //actually points to 1 after the last inst 231 inst->setInROB(); 236 assert((*tail) == inst); [all...] |
H A D | fetch_impl.hh | 287 .desc("Number of inst fetches per cycle") 559 const DynInstPtr &inst, TheISA::PCState &nextPC) 566 if (!inst->isControl()) { 567 TheISA::advancePC(nextPC, inst->staticInst); 568 inst->setPredTarg(nextPC); 569 inst->setPredTaken(false); 573 ThreadID tid = inst->threadNumber; 574 predict_taken = branchPred->predict(inst->staticInst, inst->seqNum, 580 tid, inst 558 lookupAndUpdateNextPC( const DynInstPtr &inst, TheISA::PCState &nextPC) argument 969 const auto& inst = fetchQueue[tid].front(); local 1288 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); local [all...] |
/gem5/src/arch/riscv/ |
H A D | utility.hh | 172 advancePC(PCState &pc, const StaticInstPtr &inst) argument 174 inst->advancePC(pc);
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/gem5/src/arch/alpha/ |
H A D | faults.hh | 52 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 112 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 146 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 164 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 242 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 258 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
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H A D | utility.hh | 108 advancePC(PCState &pc, const StaticInstPtr &inst) argument
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/gem5/src/arch/arm/ |
H A D | nativetrace.cc | 204 StaticInstPtr inst = record->getStaticInst(); local 205 assert(inst); 207 if (inst->isMicroop()) { 209 inst = record->getMacroStaticInst(); 211 assert(inst); 212 record->traceInst(inst, ran);
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H A D | faults.hh | 213 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 215 void invoke64(ThreadContext *tc, const StaticInstPtr &inst = 219 ArmStaticInst *instrAnnotate(const StaticInstPtr &inst); 283 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 311 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 329 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 343 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 443 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 517 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 558 void invoke(ThreadContext *tc, const StaticInstPtr &inst [all...] |
/gem5/src/arch/sparc/ |
H A D | faults.hh | 74 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 102 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 216 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 229 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 248 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 265 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 282 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
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/gem5/src/cpu/minor/ |
H A D | lsq.hh | 129 MinorDynInstPtr inst; member in class:Minor::LSQ::LSQRequest 630 void clearMemBarrier(MinorDynInstPtr inst); 669 LSQRequestPtr findResponse(MinorDynInstPtr inst); 689 void issuedMemBarrierInst(MinorDynInstPtr inst); 704 void completeMemBarrierInst(MinorDynInstPtr inst, 709 Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, 717 void pushFailedRequest(MinorDynInstPtr inst);
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H A D | dyn_inst.hh | 151 std::ostream &operator <<(std::ostream &os, const MinorDynInst &inst); 178 /** Tried to predict the destination of this inst (if a control 215 /** execSeqNum of the latest inst on which this inst depends. 249 /** There is a single bubble inst */ 291 std::ostream &operator <<(std::ostream &os, const MinorDynInst &inst);
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/gem5/src/gpu-compute/ |
H A D | kernel_cfg.cc | 272 for (GPUStaticInst* inst : instructions) { 273 int inst_addr = inst->instAddr(); 275 << "]: " << inst->disassemble(); 276 if (inst->isBranch()) { 277 std::cout << ", PC = " << inst->getTargetPc();
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/gem5/src/cpu/ |
H A D | timing_expr.cc | 47 inst(inst_), thread(thread_), let(let_) 61 return context.inst->srcRegIdx(index).index(); 71 TimingExprEvalContext new_context(context.inst,
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