Searched refs:Port (Results 126 - 150 of 158) sorted by relevance

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/gem5/src/dev/net/
H A Di8254xGBe.hh522 Port &getPort(const std::string &if_name,
/gem5/src/gpu-compute/
H A Ddispatcher.cc254 Port &
H A Dtlb_coalescer.cc70 Port &
H A Dcompute_unit.hh421 /** Data access Port **/
694 Port &
H A Dgpu_tlb.cc134 Port &
/gem5/src/systemc/tlm_bridge/
H A Dgem5_to_tlm.cc474 ::Port &
H A Dtlm_to_gem5.cc456 ::Port &
/gem5/src/arch/arm/
H A Dtlb.hh404 Port *getTableWalkerPort() override;
H A Dtable_walker.hh829 /** Port shared by the two table walkers. */
901 Port &getPort(const std::string &if_name,
/gem5/src/mem/ruby/slicc_interface/
H A DAbstractController.cc233 Port &
/gem5/src/cpu/testers/traffic_gen/
H A Dbase.cc93 Port &
/gem5/src/learning_gem5/part2/
H A Dsimple_cache.cc54 Port &
/gem5/src/arch/x86/
H A Dtlb.cc516 Port *
H A Dpagetable_walker.cc170 Port &
/gem5/src/dev/
H A Ddma_device.cc281 Port &
/gem5/src/mem/
H A Ddram_ctrl.hh1182 Port &getPort(const std::string &if_name,
H A Dxbar.cc79 Port &
H A Dcomm_monitor.cc86 Port &
/gem5/src/sim/
H A Dsystem.cc224 Port &
/gem5/src/mem/ruby/system/
H A DRubyPort.cc90 Port &
/gem5/src/dev/arm/
H A Dgic_v3_its.hh101 Port & getPort(const std::string &if_name, PortID idx) override;
H A Dsmmu_v3.cc817 Port&
/gem5/src/mem/cache/
H A Dbase.hh1056 Port &getPort(const std::string &if_name,
/gem5/src/python/m5/
H A DSimObject.py71 isNullPointer, SimObjectVector, Port
536 elif isinstance(val, Port):
/gem5/src/systemc/core/
H A Dsc_module.cc118 ::Port &

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