Searched refs:MasterPort (Results 76 - 99 of 99) sorted by relevance

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/gem5/src/cpu/kvm/
H A D	base.hh	576 * KVM memory port. Uses default MasterPort behavior and provides an 579 class KVMCpuPort : public MasterPort 584 : MasterPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
/gem5/src/gpu-compute/
H A D	gpu_tlb.hh	286 class MemSidePort : public MasterPort 291 : MasterPort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
H A D	compute_unit.cc	1856 } else if (!MasterPort::sendTimingReq(pkt)) { 1900 if (!MasterPort::sendTimingReq(packet)) {
/gem5/src/cpu/simple/
H A D	timing.hh	160 class TimingCPUPort : public MasterPort 165 : MasterPort(_name, _cpu), cpu(_cpu),
H A D	atomic.cc	278 AtomicSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt)
/gem5/src/mem/
H A D	snoop_filter.hh	184 * @param req_port MasterPort through which the response is forwarded. 187 const MasterPort& req_port);
H A D	port_proxy.hh	105 PortProxy(const MasterPort &port, unsigned int cacheLineSize) :
H A D	xbar.cc	606 * file, but since there are only two given options (MasterPort and 609 template class BaseXBar::Layer<SlavePort, MasterPort>; 610 template class BaseXBar::Layer<MasterPort, SlavePort>;
H A D	bridge.cc	73 : MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
H A D	serial_link.cc	78 : MasterPort(_name, &_serial_link), serial_link(_serial_link),
H A D	coherent_xbar.cc	72 MasterPort* bp = new CoherentXBarMasterPort(portName, *this, i); 85 MasterPort* bp = new CoherentXBarMasterPort(portName, *this, 443 MasterPort *src_port = masterPorts[master_port_id]; 593 MasterPort* snoop_port = snoopRespPorts[slave_port_id];
H A D	snoop_filter.cc	302 const SlavePort& rsp_port, const MasterPort& req_port)
/gem5/src/cpu/checker/
H A D	cpu.hh	104 void setIcachePort(MasterPort *icache_port); 106 void setDcachePort(MasterPort *dcache_port); 132 MasterPort *icachePort; 133 MasterPort *dcachePort;
/gem5/src/cpu/
H A D	BaseCPU.py	212 icache_port = MasterPort("Instruction Port") 213 dcache_port = MasterPort("Data Port")
H A D	base.hh	169 auto port = dynamic_cast<MasterPort *>(&getDataPort());
/gem5/src/cpu/o3/
H A D	lsq.hh	124 class DcachePort : public MasterPort 135 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), 1054 MasterPort &getDataPort() { return dcachePort; }
H A D	lsq_unit.hh	237 void setDcachePort(MasterPort *dcache_port); 397 MasterPort *dcachePort;
H A D	lsq_unit_impl.hh	251 LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port)
/gem5/src/dev/arm/
H A D	gic_v3_its.hh	82 class DataPort : public MasterPort 89 MasterPort(_name, &_its),
H A D	Gic.py	182 dma = MasterPort("DMA port")
/gem5/src/dev/
H A D	dma_device.hh	59 class DmaPort : public MasterPort, public Drainable
H A D	dma_device.cc	59 : MasterPort(dev->name() + ".dma", dev),
/gem5/src/mem/cache/
H A D	base.hh	86 class MasterPort; 173 CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
/gem5/src/python/m5/
H A D	params.py	2154 MasterPort = RequestPort variable 2191 'Port', 'RequestPort', 'ResponsePort', 'MasterPort', 'SlavePort',

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Indexes created Thu Sep 26 06:36:22 EDT 2019