Searched refs:MasterPort (Results 26 - 50 of 99) sorted by relevance

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/gem5/src/cpu/testers/memtest/
H A D	MemTest.py	69 port = MasterPort("Port to the memory system")
H A D	memtest.hh	98 class CpuPort : public MasterPort 105 : MasterPort(_name, &_memtest), memtest(_memtest)
/gem5/src/mem/ruby/slicc_interface/
H A D	Controller.py	72 memory = MasterPort("Port for attaching a memory controller")
/gem5/src/cpu/testers/garnet_synthetic_traffic/
H A D	GarnetSyntheticTraffic.hh	79 class CpuPort : public MasterPort 86 : MasterPort(_name, _tester), tester(_tester)
/gem5/src/mem/
H A D	qport.hh	108 class QueuedMasterPort : public MasterPort 136 MasterPort(name, owner, id), reqQueue(req_queue),
H A D	se_translating_port_proxy.hh	85 SETranslatingPortProxy(MasterPort &port, Process* p, AllocType alloc);
H A D	noncoherent_xbar.hh	143 class NoncoherentXBarMasterPort : public MasterPort 154 : MasterPort(_name, &_xbar, _id), xbar(_xbar)
H A D	addr_mapper.hh	103 class MapperMasterPort : public MasterPort 109 : MasterPort(_name, &_mapper), mapper(_mapper)
H A D	mem_checker_monitor.hh	95 class MonitorMasterPort : public MasterPort 101 : MasterPort(_name, &_mon), mon(_mon)
/gem5/src/mem/ruby/system/
H A D	Sequencer.py	42 pio_master_port = MasterPort("Ruby mem master port") 43 mem_master_port = MasterPort("Ruby mem master port")
/gem5/src/learning_gem5/part2/
H A D	simple_memobj.hh	135 class MemSidePort : public MasterPort 149 MasterPort(name, owner), owner(owner), blockedPacket(nullptr)
H A D	simple_cache.hh	142 class MemSidePort : public MasterPort 156 MasterPort(name, owner), owner(owner), blockedPacket(nullptr)
/gem5/src/cpu/simple/
H A D	atomic.hh	106 virtual Tick sendPacket(MasterPort &port, const PacketPtr &pkt); 114 class AtomicCPUPort : public MasterPort 120 : MasterPort(_name, _cpu)
/gem5/src/gpu-compute/
H A D	GPU.py	109 sqc_port = MasterPort("Port to the SQC (I-cache") 110 sqc_tlb_port = MasterPort("Port to the TLB for the SQC (I-cache)") 133 ldsPort = MasterPort("The port that goes to the LDS") 171 translation_port = MasterPort('Port to the dispatcher TLB')
H A D	dispatcher.hh	123 class TLBPort : public MasterPort 128 : MasterPort(_name, _dispatcher), dispatcher(_dispatcher) { }
H A D	tlb_coalescer.hh	182 class MemSidePort : public MasterPort 187 : MasterPort(_name, tlb_coalescer), coalescer(tlb_coalescer),
/gem5/src/systemc/tlm_bridge/
H A D	TlmBridge.py	54 gem5 = MasterPort('gem5 master port')
H A D	tlm_to_gem5.hh	95 class BridgeMasterPort : public MasterPort 111 MasterPort(name_, nullptr), bridge(bridge_)
/gem5/src/dev/arm/
H A D	smmu_v3_ports.hh	49 class SMMUMasterPort : public MasterPort 63 class SMMUMasterTableWalkPort : public MasterPort
H A D	SMMUv3.py	50 ats_master = MasterPort('ATS master port') 80 master = MasterPort('Master port') 81 master_walker = MasterPort(
H A D	smmu_v3_ports.cc	47 MasterPort(_name, &_smmu), 65 MasterPort(_name, &_smmu),
/gem5/src/cpu/minor/
H A D	cpu.hh	100 class MinorCPUPort : public MasterPort 108 : MasterPort(name_, &cpu_), cpu(cpu_)
/gem5/src/cpu/trace/
H A D	trace_cpu.hh	72 * defined. It has two port subclasses inherited from MasterPort for 228 class IcachePort : public MasterPort 233 : MasterPort(_cpu->name() + ".icache_port", _cpu), 268 class DcachePort : public MasterPort 274 : MasterPort(_cpu->name() + ".dcache_port", _cpu), 430 MasterPort& _port, MasterID master_id, 508 MasterPort& port; 857 MasterPort& _port, MasterID master_id, 994 MasterPort& port;
/gem5/src/cpu/testers/directedtest/
H A D	SeriesRequestGenerator.cc	58 MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
H A D	InvalidateGenerator.cc	57 MasterPort* port;

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Indexes created Thu Sep 26 06:36:22 EDT 2019