114039Sstacze01@arm.com/* 214039Sstacze01@arm.com * Copyright (c) 2013, 2018-2019 ARM Limited 314039Sstacze01@arm.com * All rights reserved 414039Sstacze01@arm.com * 514039Sstacze01@arm.com * The license below extends only to copyright in the software and shall 614039Sstacze01@arm.com * not be construed as granting a license to any other intellectual 714039Sstacze01@arm.com * property including but not limited to intellectual property relating 814039Sstacze01@arm.com * to a hardware implementation of the functionality of the software 914039Sstacze01@arm.com * licensed hereunder. You may use the software subject to the license 1014039Sstacze01@arm.com * terms below provided that you ensure that this notice is replicated 1114039Sstacze01@arm.com * unmodified and in its entirety in all distributions of the software, 1214039Sstacze01@arm.com * modified or unmodified, in source code or in binary form. 1314039Sstacze01@arm.com * 1414039Sstacze01@arm.com * Redistribution and use in source and binary forms, with or without 1514039Sstacze01@arm.com * modification, are permitted provided that the following conditions are 1614039Sstacze01@arm.com * met: redistributions of source code must retain the above copyright 1714039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer; 1814039Sstacze01@arm.com * redistributions in binary form must reproduce the above copyright 1914039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer in the 2014039Sstacze01@arm.com * documentation and/or other materials provided with the distribution; 2114039Sstacze01@arm.com * neither the name of the copyright holders nor the names of its 2214039Sstacze01@arm.com * contributors may be used to endorse or promote products derived from 2314039Sstacze01@arm.com * this software without specific prior written permission. 2414039Sstacze01@arm.com * 2514039Sstacze01@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2614039Sstacze01@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2714039Sstacze01@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2814039Sstacze01@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2914039Sstacze01@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3014039Sstacze01@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3114039Sstacze01@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3214039Sstacze01@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3314039Sstacze01@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3414039Sstacze01@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3514039Sstacze01@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3614039Sstacze01@arm.com * 3714039Sstacze01@arm.com * Authors: Stan Czerniawski 3814039Sstacze01@arm.com */ 3914039Sstacze01@arm.com 4014039Sstacze01@arm.com#include "dev/arm/smmu_v3_ports.hh" 4114039Sstacze01@arm.com 4214039Sstacze01@arm.com#include "base/logging.hh" 4314039Sstacze01@arm.com#include "dev/arm/smmu_v3.hh" 4414039Sstacze01@arm.com#include "dev/arm/smmu_v3_slaveifc.hh" 4514039Sstacze01@arm.com 4614039Sstacze01@arm.comSMMUMasterPort::SMMUMasterPort(const std::string &_name, SMMUv3 &_smmu) : 4714039Sstacze01@arm.com MasterPort(_name, &_smmu), 4814039Sstacze01@arm.com smmu(_smmu) 4914039Sstacze01@arm.com{} 5014039Sstacze01@arm.com 5114039Sstacze01@arm.combool 5214039Sstacze01@arm.comSMMUMasterPort::recvTimingResp(PacketPtr pkt) 5314039Sstacze01@arm.com{ 5414039Sstacze01@arm.com return smmu.masterRecvTimingResp(pkt); 5514039Sstacze01@arm.com} 5614039Sstacze01@arm.com 5714039Sstacze01@arm.comvoid 5814039Sstacze01@arm.comSMMUMasterPort::recvReqRetry() 5914039Sstacze01@arm.com{ 6014039Sstacze01@arm.com return smmu.masterRecvReqRetry(); 6114039Sstacze01@arm.com} 6214039Sstacze01@arm.com 6314039Sstacze01@arm.comSMMUMasterTableWalkPort::SMMUMasterTableWalkPort(const std::string &_name, 6414039Sstacze01@arm.com SMMUv3 &_smmu) : 6514039Sstacze01@arm.com MasterPort(_name, &_smmu), 6614039Sstacze01@arm.com smmu(_smmu) 6714039Sstacze01@arm.com{} 6814039Sstacze01@arm.com 6914039Sstacze01@arm.combool 7014039Sstacze01@arm.comSMMUMasterTableWalkPort::recvTimingResp(PacketPtr pkt) 7114039Sstacze01@arm.com{ 7214039Sstacze01@arm.com return smmu.masterTableWalkRecvTimingResp(pkt); 7314039Sstacze01@arm.com} 7414039Sstacze01@arm.com 7514039Sstacze01@arm.comvoid 7614039Sstacze01@arm.comSMMUMasterTableWalkPort::recvReqRetry() 7714039Sstacze01@arm.com{ 7814039Sstacze01@arm.com return smmu.masterTableWalkRecvReqRetry(); 7914039Sstacze01@arm.com} 8014039Sstacze01@arm.com 8114039Sstacze01@arm.comSMMUSlavePort::SMMUSlavePort(const std::string &_name, 8214039Sstacze01@arm.com SMMUv3SlaveInterface &_ifc, 8314039Sstacze01@arm.com PortID _id) 8414039Sstacze01@arm.com: 8514039Sstacze01@arm.com QueuedSlavePort(_name, &_ifc, respQueue, _id), 8614039Sstacze01@arm.com ifc(_ifc), 8714039Sstacze01@arm.com respQueue(_ifc, *this) 8814039Sstacze01@arm.com{} 8914039Sstacze01@arm.com 9014039Sstacze01@arm.comvoid 9114039Sstacze01@arm.comSMMUSlavePort::recvFunctional(PacketPtr pkt) 9214039Sstacze01@arm.com{ 9314039Sstacze01@arm.com if (!respQueue.trySatisfyFunctional(pkt)) 9414039Sstacze01@arm.com recvAtomic(pkt); 9514039Sstacze01@arm.com} 9614039Sstacze01@arm.com 9714039Sstacze01@arm.comTick 9814039Sstacze01@arm.comSMMUSlavePort::recvAtomic(PacketPtr pkt) 9914039Sstacze01@arm.com{ 10014039Sstacze01@arm.com return ifc.recvAtomic(pkt); 10114039Sstacze01@arm.com} 10214039Sstacze01@arm.com 10314039Sstacze01@arm.combool 10414039Sstacze01@arm.comSMMUSlavePort::recvTimingReq(PacketPtr pkt) 10514039Sstacze01@arm.com{ 10614039Sstacze01@arm.com return ifc.recvTimingReq(pkt); 10714039Sstacze01@arm.com} 10814039Sstacze01@arm.com 10914039Sstacze01@arm.comSMMUControlPort::SMMUControlPort(const std::string &_name, 11014039Sstacze01@arm.com SMMUv3 &_smmu, AddrRange _addrRange) 11114039Sstacze01@arm.com: 11214039Sstacze01@arm.com SimpleTimingPort(_name, &_smmu), 11314039Sstacze01@arm.com smmu(_smmu), 11414039Sstacze01@arm.com addrRange(_addrRange) 11514039Sstacze01@arm.com{} 11614039Sstacze01@arm.com 11714039Sstacze01@arm.comTick 11814039Sstacze01@arm.comSMMUControlPort::recvAtomic(PacketPtr pkt) 11914039Sstacze01@arm.com{ 12014039Sstacze01@arm.com Addr addr = pkt->getAddr(); 12114039Sstacze01@arm.com unsigned size = pkt->getSize(); 12214039Sstacze01@arm.com 12314039Sstacze01@arm.com if (!addrRange.contains(addr) || !addrRange.contains(addr+size)) 12414039Sstacze01@arm.com panic("SMMU: invalid address on control port %x, packet size %d", 12514039Sstacze01@arm.com addr, size); 12614039Sstacze01@arm.com 12714039Sstacze01@arm.com // @todo: We need to pay for this and not just zero it out 12814039Sstacze01@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 12914039Sstacze01@arm.com 13014039Sstacze01@arm.com return pkt->isRead() ? smmu.readControl(pkt) : smmu.writeControl(pkt); 13114039Sstacze01@arm.com} 13214039Sstacze01@arm.com 13314039Sstacze01@arm.comAddrRangeList 13414039Sstacze01@arm.comSMMUControlPort::getAddrRanges() const 13514039Sstacze01@arm.com{ 13614039Sstacze01@arm.com AddrRangeList list; 13714039Sstacze01@arm.com list.push_back(addrRange); 13814039Sstacze01@arm.com return list; 13914039Sstacze01@arm.com} 14014039Sstacze01@arm.com 14114039Sstacze01@arm.comSMMUATSMasterPort::SMMUATSMasterPort(const std::string &_name, 14214039Sstacze01@arm.com SMMUv3SlaveInterface &_ifc) : 14314039Sstacze01@arm.com QueuedMasterPort(_name, &_ifc, reqQueue, snoopRespQueue), 14414039Sstacze01@arm.com ifc(_ifc), 14514039Sstacze01@arm.com reqQueue(_ifc, *this), 14614039Sstacze01@arm.com snoopRespQueue(_ifc, *this) 14714039Sstacze01@arm.com{} 14814039Sstacze01@arm.com 14914039Sstacze01@arm.combool 15014039Sstacze01@arm.comSMMUATSMasterPort::recvTimingResp(PacketPtr pkt) 15114039Sstacze01@arm.com{ 15214039Sstacze01@arm.com return ifc.atsMasterRecvTimingResp(pkt); 15314039Sstacze01@arm.com} 15414039Sstacze01@arm.com 15514039Sstacze01@arm.comSMMUATSSlavePort::SMMUATSSlavePort(const std::string &_name, 15614039Sstacze01@arm.com SMMUv3SlaveInterface &_ifc) : 15714039Sstacze01@arm.com QueuedSlavePort(_name, &_ifc, respQueue), 15814039Sstacze01@arm.com ifc(_ifc), 15914039Sstacze01@arm.com respQueue(_ifc, *this) 16014039Sstacze01@arm.com{} 16114039Sstacze01@arm.com 16214039Sstacze01@arm.comvoid 16314039Sstacze01@arm.comSMMUATSSlavePort::recvFunctional(PacketPtr pkt) 16414039Sstacze01@arm.com{ 16514039Sstacze01@arm.com panic("Functional access on ATS port!"); 16614039Sstacze01@arm.com} 16714039Sstacze01@arm.com 16814039Sstacze01@arm.comTick 16914039Sstacze01@arm.comSMMUATSSlavePort::recvAtomic(PacketPtr pkt) 17014039Sstacze01@arm.com{ 17114039Sstacze01@arm.com return ifc.atsSlaveRecvAtomic(pkt); 17214039Sstacze01@arm.com} 17314039Sstacze01@arm.com 17414039Sstacze01@arm.combool 17514039Sstacze01@arm.comSMMUATSSlavePort::recvTimingReq(PacketPtr pkt) 17614039Sstacze01@arm.com{ 17714039Sstacze01@arm.com return ifc.atsSlaveRecvTimingReq(pkt); 17814039Sstacze01@arm.com} 179