12381SN/A/*
210719SMarco.Balboni@ARM.com * Copyright (c) 2011-2015 ARM Limited
38711SN/A * All rights reserved
48711SN/A *
58711SN/A * The license below extends only to copyright in the software and shall
68711SN/A * not be construed as granting a license to any other intellectual
78711SN/A * property including but not limited to intellectual property relating
88711SN/A * to a hardware implementation of the functionality of the software
98711SN/A * licensed hereunder.  You may use the software subject to the license
108711SN/A * terms below provided that you ensure that this notice is replicated
118711SN/A * unmodified and in its entirety in all distributions of the software,
128711SN/A * modified or unmodified, in source code or in binary form.
138711SN/A *
142381SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
152381SN/A * All rights reserved.
162381SN/A *
172381SN/A * Redistribution and use in source and binary forms, with or without
182381SN/A * modification, are permitted provided that the following conditions are
192381SN/A * met: redistributions of source code must retain the above copyright
202381SN/A * notice, this list of conditions and the following disclaimer;
212381SN/A * redistributions in binary form must reproduce the above copyright
222381SN/A * notice, this list of conditions and the following disclaimer in the
232381SN/A * documentation and/or other materials provided with the distribution;
242381SN/A * neither the name of the copyright holders nor the names of its
252381SN/A * contributors may be used to endorse or promote products derived from
262381SN/A * this software without specific prior written permission.
272381SN/A *
282381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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382381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665SN/A *
402665SN/A * Authors: Ron Dreslinski
412772SN/A *          Ali Saidi
428715SN/A *          Andreas Hansson
438922SN/A *          William Wang
442381SN/A */
452381SN/A
462381SN/A/**
472982SN/A * @file
4810405Sandreas.hansson@arm.com * Declaration of a non-coherent crossbar.
492381SN/A */
502381SN/A
5110405Sandreas.hansson@arm.com#ifndef __MEM_NONCOHERENT_XBAR_HH__
5210405Sandreas.hansson@arm.com#define __MEM_NONCOHERENT_XBAR_HH__
532381SN/A
5410405Sandreas.hansson@arm.com#include "mem/xbar.hh"
5510405Sandreas.hansson@arm.com#include "params/NoncoherentXBar.hh"
562381SN/A
579036SN/A/**
5810405Sandreas.hansson@arm.com * A non-coherent crossbar connects a number of non-snooping masters
5910405Sandreas.hansson@arm.com * and slaves, and routes the request and response packets based on
6010405Sandreas.hansson@arm.com * the address. The request packets issued by the master connected to
6110405Sandreas.hansson@arm.com * a non-coherent crossbar could still snoop in caches attached to a
6210405Sandreas.hansson@arm.com * coherent crossbar, as is the case with the I/O bus and memory bus
6310405Sandreas.hansson@arm.com * in most system configurations. No snoops will, however, reach any
6410405Sandreas.hansson@arm.com * master on the non-coherent crossbar itself.
659036SN/A *
6610405Sandreas.hansson@arm.com * The non-coherent crossbar can be used as a template for modelling
679036SN/A * PCIe, and non-coherent AMBA and OCP buses, and is typically used
689036SN/A * for the I/O buses.
699036SN/A */
7010405Sandreas.hansson@arm.comclass NoncoherentXBar : public BaseXBar
712381SN/A{
729031SN/A
739036SN/A  protected:
749036SN/A
758922SN/A    /**
7610405Sandreas.hansson@arm.com     * Declare the layers of this crossbar, one vector for requests
7710405Sandreas.hansson@arm.com     * and one for responses.
789092SN/A     */
799715SN/A    std::vector<ReqLayer*> reqLayers;
809715SN/A    std::vector<RespLayer*> respLayers;
819092SN/A
829092SN/A    /**
8310405Sandreas.hansson@arm.com     * Declaration of the non-coherent crossbar slave port type, one
8410405Sandreas.hansson@arm.com     * will be instantiated for each of the master ports connecting to
8510405Sandreas.hansson@arm.com     * the crossbar.
868922SN/A     */
8710888Sandreas.hansson@arm.com    class NoncoherentXBarSlavePort : public QueuedSlavePort
882381SN/A    {
898922SN/A      private:
909036SN/A
9110405Sandreas.hansson@arm.com        /** A reference to the crossbar to which this port belongs. */
9210405Sandreas.hansson@arm.com        NoncoherentXBar &xbar;
932381SN/A
9410888Sandreas.hansson@arm.com        /** A normal packet queue used to store responses. */
9510888Sandreas.hansson@arm.com        RespPacketQueue queue;
9610888Sandreas.hansson@arm.com
972381SN/A      public:
982381SN/A
9910405Sandreas.hansson@arm.com        NoncoherentXBarSlavePort(const std::string &_name,
10010405Sandreas.hansson@arm.com                                NoncoherentXBar &_xbar, PortID _id)
10110888Sandreas.hansson@arm.com            : QueuedSlavePort(_name, &_xbar, queue, _id), xbar(_xbar),
10210888Sandreas.hansson@arm.com              queue(_xbar, *this)
1038922SN/A        { }
1048922SN/A
1058922SN/A      protected:
1068922SN/A
10713808Sgabeblack@google.com        bool
10813808Sgabeblack@google.com        recvTimingReq(PacketPtr pkt) override
10913808Sgabeblack@google.com        {
11013808Sgabeblack@google.com            return xbar.recvTimingReq(pkt, id);
11113808Sgabeblack@google.com        }
1128948SN/A
11313808Sgabeblack@google.com        Tick
11413808Sgabeblack@google.com        recvAtomic(PacketPtr pkt) override
11513808Sgabeblack@google.com        {
11613847Sgabeblack@google.com            return xbar.recvAtomicBackdoor(pkt, id);
11713847Sgabeblack@google.com        }
11813847Sgabeblack@google.com
11913847Sgabeblack@google.com        Tick
12013847Sgabeblack@google.com        recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override
12113847Sgabeblack@google.com        {
12213847Sgabeblack@google.com            return xbar.recvAtomicBackdoor(pkt, id, &backdoor);
12313808Sgabeblack@google.com        }
1248922SN/A
12513808Sgabeblack@google.com        void
12613808Sgabeblack@google.com        recvFunctional(PacketPtr pkt) override
12713808Sgabeblack@google.com        {
12813808Sgabeblack@google.com            xbar.recvFunctional(pkt, id);
12913808Sgabeblack@google.com        }
1308922SN/A
13113808Sgabeblack@google.com        AddrRangeList
13213808Sgabeblack@google.com        getAddrRanges() const override
13313808Sgabeblack@google.com        {
13413808Sgabeblack@google.com            return xbar.getAddrRanges();
13513808Sgabeblack@google.com        }
1368922SN/A    };
1378922SN/A
1388922SN/A    /**
13910405Sandreas.hansson@arm.com     * Declaration of the crossbar master port type, one will be
1409036SN/A     * instantiated for each of the slave ports connecting to the
14110405Sandreas.hansson@arm.com     * crossbar.
1428922SN/A     */
14310405Sandreas.hansson@arm.com    class NoncoherentXBarMasterPort : public MasterPort
1448922SN/A    {
1458922SN/A      private:
1469036SN/A
14710405Sandreas.hansson@arm.com        /** A reference to the crossbar to which this port belongs. */
14810405Sandreas.hansson@arm.com        NoncoherentXBar &xbar;
1498922SN/A
1508922SN/A      public:
1518922SN/A
15210405Sandreas.hansson@arm.com        NoncoherentXBarMasterPort(const std::string &_name,
15310405Sandreas.hansson@arm.com                                 NoncoherentXBar &_xbar, PortID _id)
15410405Sandreas.hansson@arm.com            : MasterPort(_name, &_xbar, _id), xbar(_xbar)
1552381SN/A        { }
1562381SN/A
1572381SN/A      protected:
1582381SN/A
15913808Sgabeblack@google.com        bool
16013808Sgabeblack@google.com        recvTimingResp(PacketPtr pkt) override
16113808Sgabeblack@google.com        {
16213808Sgabeblack@google.com            return xbar.recvTimingResp(pkt, id);
16313808Sgabeblack@google.com        }
1642381SN/A
16513808Sgabeblack@google.com        void
16613808Sgabeblack@google.com        recvRangeChange() override
16713808Sgabeblack@google.com        {
16813808Sgabeblack@google.com            xbar.recvRangeChange(id);
16913808Sgabeblack@google.com        }
1702381SN/A
17113808Sgabeblack@google.com        void
17213808Sgabeblack@google.com        recvReqRetry() override
17313808Sgabeblack@google.com        {
17413808Sgabeblack@google.com            xbar.recvReqRetry(id);
17513808Sgabeblack@google.com        }
1762381SN/A    };
1772381SN/A
1789083SN/A    virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
1799083SN/A    virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
18010713Sandreas.hansson@arm.com    void recvReqRetry(PortID master_port_id);
18113847Sgabeblack@google.com    Tick recvAtomicBackdoor(PacketPtr pkt, PortID slave_port_id,
18213847Sgabeblack@google.com                            MemBackdoorPtr *backdoor=nullptr);
1839032SN/A    void recvFunctional(PacketPtr pkt, PortID slave_port_id);
1844475SN/A
1852381SN/A  public:
1862381SN/A
18710405Sandreas.hansson@arm.com    NoncoherentXBar(const NoncoherentXBarParams *p);
1882568SN/A
18910405Sandreas.hansson@arm.com    virtual ~NoncoherentXBar();
1909715SN/A
19113808Sgabeblack@google.com    void regStats() override;
19210405Sandreas.hansson@arm.com    Stats::Scalar totPktSize;
1932381SN/A};
1942381SN/A
19510405Sandreas.hansson@arm.com#endif //__MEM_NONCOHERENT_XBAR_HH__
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