Searched hist:52 (Results 976 - 992 of 992) sorted by relevance
/gem5/src/arch/sparc/ | ||
H A D | tlb.cc | 4010:52c2b6941c02 Fri Feb 02 19:02:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> more sparc fixes src/arch/sparc/isa/decoder.isa: fix rdgsr fault check src/arch/sparc/tlb.cc: block asis are now supported |
/gem5/src/arch/arm/ | ||
H A D | table_walker.cc | 12526:94adfd8b5dbd Wed Aug 02 04:52:00 EDT 2017 Chuan Zhu <chuan.zhu@arm.com> arch-arm: Fix big endian support in do{Long,L1,L2}Descriptor do{Long,L1,L2}Descriptor was not able to load descriptors correctly for big-endian situations, causing recognised Descriptors. Added big-endian related data conversions to correct them. Change-Id: I0fdfbbdf56f94bbed19172acae1b6e4a0382b5a0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8144 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/mem/ | ||
H A D | request.hh | 11294:a368064a2ab5 Mon Jan 11 05:52:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> scons: Enable -Wextra by default Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial. |
/gem5/src/cpu/simple/ | ||
H A D | timing.hh | 9830:5995f4d33a11 Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> cpu: Fix timing CPU drain check This patch modifies the SimpleTimingCPU drain check to also consider the fetch event. Previously, there was an assumption that there is never a fetch event scheduled if the CPU is not executing microcode. However, when a context is activated, a fetch even is scheduled, and microPC() is zero. |
H A D | atomic.hh | 12127:4207df055b0d Wed Jun 28 09:52:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> cpu: Refactor some Event subclasses to lambdas Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3923 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
H A D | base.cc | 4572:5499df089a6c Thu Jun 14 16:52:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> Modified instruction decode method. Make code compatible with new decode method. src/arch/alpha/remote_gdb.cc: src/cpu/base_dyn_inst_impl.hh: src/cpu/exetrace.cc: src/cpu/simple/base.cc: Make code compatible with new decode method. src/cpu/static_inst.cc: src/cpu/static_inst.hh: Modified instruction decode method. 4240:cde9d7751cce Wed Mar 14 22:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/arch/mips/utility.hh: src/arch/x86/SConscript: Hand merge |
H A D | base.hh | 4240:cde9d7751cce Wed Mar 14 22:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/arch/mips/utility.hh: src/arch/x86/SConscript: Hand merge |
/gem5/src/cpu/o3/ | ||
H A D | commit_impl.hh | 12127:4207df055b0d Wed Jun 28 09:52:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> cpu: Refactor some Event subclasses to lambdas Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3923 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 3970:d54945bab95d Wed Jan 03 00:52:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem |
H A D | commit.hh | 12127:4207df055b0d Wed Jun 28 09:52:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> cpu: Refactor some Event subclasses to lambdas Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3923 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
H A D | inst_queue_impl.hh | 10797:855cafd64da1 Wed Apr 22 10:52:00 EDT 2015 Brandon Potter <brandon.potter@amd.com> cpu: remove conditional check (count > 0) on o3 IQ squashes The o3 cpu instruction queue model uses the count variable to track the number of unissued instructions in the queue. Previously, the squash method used this variable to avoid executing the doSquash method when there were no unissued instructions in the pipeline. A corner case problem exists when only issued instructions exist in the pipeline and a squash occurs; the doSquash code is not invoked and subsequently does not clean up state properly. |
H A D | iew_impl.hh | 3970:d54945bab95d Wed Jan 03 00:52:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem |
/gem5/src/mem/cache/ | ||
H A D | base.cc | 12754:15c1d281ce1a Wed Jun 06 08:52:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Insert on block allocation When a block is being replaced in an allocation, if successfull, the block will be inserted. Therefore we move the insertion functionality to allocateBlock(). allocateBlock's signature has been modified to allow this modification. Change-Id: I60d17a83ff4f3021fdc976378868ccde6c7507bc Reviewed-on: https://gem5-review.googlesource.com/10812 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> 8856:241ee47b0dc6 Fri Feb 24 11:52:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Simplify cache ports preparing for master/slave split This patch splits the two cache ports into a master (memory-side) and slave (cpu-side) subclass of port with slightly different functionality. For example, it is only the CPU-side port that blocks incoming requests, and only the memory-side port that schedules send events outside of what the transmit list dictates. This patch simplifies the two classes by relying further on SimpleTimingPort and also generalises the latter to better accommodate the changes (introducing trySendTiming and scheduleSend). The memory-side cache port overrides sendDeferredPacket to be able to not only send responses from the transmit list, but also send requests based on the MSHRs. A follow on patch further simplifies the SimpleTimingPort and the cache ports. |
/gem5/src/cpu/ | ||
H A D | thread_context.hh | 2682:52ac6338355d Wed Jun 07 15:17:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Move checker's exec_context.hh to match the other changes. Also add in some more comments. src/cpu/thread_context.hh: Add more comments. |
H A D | base_dyn_inst.hh | 11294:a368064a2ab5 Mon Jan 11 05:52:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> scons: Enable -Wextra by default Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial. |
/gem5/src/sim/ | ||
H A D | system.hh | 11911:fecd8de0ec8e Wed Mar 01 15:52:00 EST 2017 Brandon Potter <Brandon.Potter@amd.com> syscall-emul: Rewrite system call exit code The changeset does a major refactor on the exit, exit_group, and futex system calls regarding exit functionality. A FutexMap class and related structures are added into a new file. This increases code clarity by encapsulating the futex operations and the futex state into an object. Several exit conditions were added to allow the simulator to end processes under certain conditions. Also, the simulation only exits now when all processes have finished executing. Change-Id: I1ee244caa9b5586fe7375e5b9b50fd3959b9655e Reviewed-on: https://gem5-review.googlesource.com/2269 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
H A D | syscall_emul.cc | 11911:fecd8de0ec8e Wed Mar 01 15:52:00 EST 2017 Brandon Potter <Brandon.Potter@amd.com> syscall-emul: Rewrite system call exit code The changeset does a major refactor on the exit, exit_group, and futex system calls regarding exit functionality. A FutexMap class and related structures are added into a new file. This increases code clarity by encapsulating the futex operations and the futex state into an object. Several exit conditions were added to allow the simulator to end processes under certain conditions. Also, the simulation only exits now when all processes have finished executing. Change-Id: I1ee244caa9b5586fe7375e5b9b50fd3959b9655e Reviewed-on: https://gem5-review.googlesource.com/2269 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/dev/arm/ | ||
H A D | RealView.py | 9835:cc7a7fc71c42 Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Change AbstractMemory defaults to match the common case This patch changes the default parameter value of conf_table_reported to match the common case. It also simplifies the regression and config scripts to reflect this change. |
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