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/gem5/src/systemc/tests/ | ||
H A D | verify.py | 12903:f81321fad993 Fri Jun 15 18:52:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add a filter-file option. The --filter option is very useful, but can get to be long and complex and a bit too cumbersome to use from the command line. This change adds a --filter-file option which is mutually exclusive with --filter and which reads the filter expression from a file instead of accepting it on the command line. Change-Id: I381c92ddf0d9fe62acd20432fa4868e2121405b8 Reviewed-on: https://gem5-review.googlesource.com/11257 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/tests/configs/ | ||
H A D | memtest.py | 9827:f47274776aa0 Mon Aug 19 03:52:00 EDT 2013 Akash Bagdia <akash.bagdia@arm.com> power: Add voltage domains to the clock domains This patch adds the notion of voltage domains, and groups clock domains that operate under the same voltage (i.e. power supply) into domains. Each clock domain is required to be associated with a voltage domain, and the latter requires the voltage to be explicitly set. A voltage domain is an independently controllable voltage supply being provided to section of the design. Thus, if you wish to perform dynamic voltage scaling on a CPU, its clock domain should be associated with a separate voltage domain. The current implementation of the voltage domain does not take into consideration cases where there are derived voltage domains running at ratio of native voltage domains, as with the case where there can be on-chip buck/boost (charge pumps) voltage regulation logic. The regression and configuration scripts are updated with a generic voltage domain for the system, and one for the CPUs. |
/gem5/src/arch/ | ||
H A D | SConscript | 4240:cde9d7751cce Wed Mar 14 22:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/arch/mips/utility.hh: src/arch/x86/SConscript: Hand merge |
/gem5/src/arch/arm/ | ||
H A D | process.cc | 6400:b7fd31c84c99 Mon Jul 27 03:52:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Set up the initial stack frame to match a recent Linux. |
H A D | system.cc | 8885:52bbd95b31ed Fri Mar 09 09:59:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> System: Move code in initState() back into constructor whenever possible. The change to port proxies recently moved code out of the constructor into initState(). This is needed for code that loads data into memory, however for code that setups symbol tables, kernel based events, etc this is the wrong thing to do as that code is only called when a checkpoint isn't being restored from. |
H A D | faults.hh | 11294:a368064a2ab5 Mon Jan 11 05:52:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> scons: Enable -Wextra by default Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial. |
/gem5/configs/ruby/ | ||
H A D | MOESI_hammer.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
H A D | MOESI_CMP_token.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
H A D | MOESI_CMP_directory.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
/gem5/src/arch/alpha/linux/ | ||
H A D | process.cc | 13983:0faf12cff9c4 Fri May 03 01:52:00 EDT 2019 Gabe Black <gabeblack@google.com> alpha: Add an object file loader for linux. Change-Id: I91c4019567bdf74b2517fda597121a6ad107cb86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18584 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
H A D | system.cc | 8885:52bbd95b31ed Fri Mar 09 09:59:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> System: Move code in initState() back into constructor whenever possible. The change to port proxies recently moved code out of the constructor into initState(). This is needed for code that loads data into memory, however for code that setups symbol tables, kernel based events, etc this is the wrong thing to do as that code is only called when a checkpoint isn't being restored from. |
/gem5/src/arch/alpha/ | ||
H A D | stacktrace.cc | 3570:aacc19068f25 Wed Nov 08 00:52:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Put the ProcessInfo and StackTrace objects into the ISA namespaces. |
/gem5/src/base/loader/ | ||
H A D | elf_object.cc | 8350:9fb150de362e Mon Jun 13 02:52:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Loader: Handle bad section names when loading an ELF file. If there's a problem when reading the section names from a supposed ELF file, this change makes gem5 print an error message as returned by libelf and die. Previously these sorts of errors would make gem5 segfault when it tried to access the section name through a NULL pointer. |
/gem5/src/cpu/ | ||
H A D | base_dyn_inst_impl.hh | 4572:5499df089a6c Thu Jun 14 16:52:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> Modified instruction decode method. Make code compatible with new decode method. src/arch/alpha/remote_gdb.cc: src/cpu/base_dyn_inst_impl.hh: src/cpu/exetrace.cc: src/cpu/simple/base.cc: Make code compatible with new decode method. src/cpu/static_inst.cc: src/cpu/static_inst.hh: Modified instruction decode method. |
H A D | base.hh | 12127:4207df055b0d Wed Jun 28 09:52:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> cpu: Refactor some Event subclasses to lambdas Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3923 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 9817:2492d7ccda7e Fri Jul 19 05:52:00 EDT 2013 Andreas Sandberg <andreas@sandberg.pp.se> cpu: Remove unused getBranchPred() method from BaseCPU Remove unused virtual getBranchPred() method from BaseCPU as it is not implemented by any of the CPU models. It used to always return NULL. 4240:cde9d7751cce Wed Mar 14 22:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/arch/mips/utility.hh: src/arch/x86/SConscript: Hand merge 3541:d74340b852f6 Mon Nov 06 19:52:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem/ into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops src/SConscript: SCCS merged |
/gem5/src/mem/ | ||
H A D | abstract_mem.cc | 13998:2feca2ebe67b Wed Dec 12 16:52:00 EST 2018 Tiago Muck <tiago.muck@arm.com> mem: Add invalid context id check on LLSC checks If the request's address is in the LLSC list, its context Id was being fetched unconditionally, which could cause the assert at Request::contextId() to fail. Change-Id: Iae9791f81c8fe9a7fcd842cd8ab7db18f34f2808 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18792 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
H A D | simple_mem.cc | 9823:c8dd3368c6ba Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Add an internal packet queue in SimpleMemory This patch adds a packet queue in SimpleMemory to avoid using the packet queue in the port (and thus have no involvement in the flow control). The port queue was bound to 100 packets, and as the SimpleMemory is modelling both a controller and an actual RAM, it potentially has a large number of packets in flight. There is currently no limit on the number of packets in the memory controller, but this could easily be added in a follow-on patch. As a result of the added internal storage, the functional access and draining is updated. Some minor cleaning up and renaming has also been done. The memtest regression changes as a result of this patch and the stats will be updated. |
H A D | tport.cc | 8856:241ee47b0dc6 Fri Feb 24 11:52:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Simplify cache ports preparing for master/slave split This patch splits the two cache ports into a master (memory-side) and slave (cpu-side) subclass of port with slightly different functionality. For example, it is only the CPU-side port that blocks incoming requests, and only the memory-side port that schedules send events outside of what the transmit list dictates. This patch simplifies the two classes by relying further on SimpleTimingPort and also generalises the latter to better accommodate the changes (introducing trySendTiming and scheduleSend). The memory-side cache port overrides sendDeferredPacket to be able to not only send responses from the transmit list, but also send requests based on the MSHRs. A follow on patch further simplifies the SimpleTimingPort and the cache ports. |
H A D | page_table.hh | 11294:a368064a2ab5 Mon Jan 11 05:52:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> scons: Enable -Wextra by default Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial. |
/gem5/src/mem/cache/ | ||
H A D | mshr.hh | 12792:9af3470e24e7 Fri Mar 16 20:52:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix promoting of targets that need writable There are cases where a request which does not need a writable copy gets an response upgraded reponse and fills in a writable copy. When this happens, we promote deferred MSHR targets that were deferred because they needed a writable copy to service them immediately. Previously, we would uncoditionally promote deferred targets. Since the deferred targets might contain a cache invalidation operation, we have to make sure that any targets following the cache invalidation is not promoted. Change-Id: I1f7b28f7d35f84329e065c8f63117db21852365a Reviewed-on: https://gem5-review.googlesource.com/11016 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/mem/cache/tags/ | ||
H A D | base.hh | 12553:514f2e4fb751 Mon Oct 31 11:52:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Remove mumBlock redundant initialiation from FALRU Change-Id: Id3afec0a62446d6d0f44ccb655032343037637e0 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8281 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/mem/ruby/slicc_interface/ | ||
H A D | AbstractController.hh | 11294:a368064a2ab5 Mon Jan 11 05:52:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> scons: Enable -Wextra by default Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial. |
/gem5/src/mem/ruby/system/ | ||
H A D | DMASequencer.cc | 6467:5670eee2a866 Tue Aug 04 01:52:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers This changeset contains a lot of different changes that are too mingled to separate. They are: 1. Added MOESI_CMP_directory I made the changes necessary to bring back MOESI_CMP_directory, including adding a DMA controller. I got rid of MOESI_CMP_directory_m and made MOESI_CMP_directory use a memory controller. Added a new configuration for two level protocols in general, and MOESI_CMP_directory in particular. 2. DMA Sequencer uses a generic SequencerMsg I will eventually make the cache Sequencer use this type as well. It doesn't contain an offset field, just a physical address and a length. MI_example has been updated to deal with this. 3. Parameterized Controllers SLICC controllers can now take custom parameters to use for mapping, latencies, etc. Currently, only int parameters are supported. |
H A D | Sequencer.hh | 6825:104115ebc206 Fri Aug 21 16:52:00 EDT 2009 pdudnik@gmail.com [mq]: first_patch |
/gem5/src/mem/slicc/symbols/ | ||
H A D | Type.py | 9219:258753d3bc47 Wed Sep 12 15:52:00 EDT 2012 Jason Power <power.jg@gmail.com> Ruby: Modify Scons so that we can put .sm files in extras Also allows for header files which are required in slicc generated code to be in a directory other than src/mem/ruby/slicc_interface. |
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