History log of /gem5/src/arch/SConscript
Revision Date Author Comments
# 13911:81ddb29c6b4c 29-Apr-2019 Gabe Black <gabeblack@google.com>

arch: Remove the mt.hh switching header.

This header was only useful in MIPS and is only used internally within
MIPS. It doesn't need to be a switching header file.

Change-Id: Id7005f73b95e122f9ab83b3b657cae3391682f26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18468
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>


# 13610:5d5404ac6288 16-Oct-2018 Giacomo Gabrielli <giacomo.gabrielli@arm.com>

arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>


# 12462:abdd0f6a2593 09-Jan-2018 Gabe Black <gabeblack@google.com>

arch: Remove the "arch/tlb.hh" switching header.

This header is no longer used.

Change-Id: I8da7f8618d647dd11c581818c13855c4e20d32d2
Reviewed-on: https://gem5-review.googlesource.com/7351
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>


# 12246:9ffa51416f39 08-Nov-2017 Gabe Black <gabeblack@google.com>

scons: Move Transform and termcap functionality into their own files.

Change-Id: Ica08e93f3873a7eafd02fe7d44c3bdbf0ce7f6b7
Reviewed-on: https://gem5-review.googlesource.com/5565
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>


# 12222:6db0fc7407a5 15-Oct-2017 Gabe Black <gabeblack@google.com>

scons: Stop generating inc.d in the isa parser.

Generating dependency/build product information in the isa parser breaks scons
idea of how a build is supposed to work. Arm twisting it into working forced
a lot of false dependencies which slowed down the build.

Change-Id: Iadee8c930fd7c80136d200d69870df7672a6b3ca
Reviewed-on: https://gem5-review.googlesource.com/5081
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>


# 12109:f29e9c5418aa 05-Apr-2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com>

cpu: Added interface for vector reg file

This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.

This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.

This requires implementing the vector register file for the different
models using the VecRegContainer class.

This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.

The changes also affect how the remote_gdb connection works.

There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.

Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.

Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705


# 12016:893091853afd 02-May-2017 Gabe Black <gabeblack@google.com>

scons: Use the generalized switching headers on the GPU ISA.

Now that the switching header implementation has been generalized, there's
no need to have two nearly identical implementations for the two different
groups of headers.

Change-Id: Ie7c24fcddbc672ac5ca2d69bfc35696f42c55580
Reviewed-on: https://gem5-review.googlesource.com/2984
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>


# 12015:469a2f126b4c 02-May-2017 Gabe Black <gabeblack@google.com>

scons: arch: Generalize the switching header code.

Factor out the ISA ness of the switching header generating function. Also
turn it into a SCons builder which builds a single header, and a wrapping
method which uses the builder on a group of header files which all target
the same subdirectory.

Change-Id: I87705f97b6ebd9baebd4ebcfea19cc1218a64ad0
Reviewed-on: https://gem5-review.googlesource.com/2983
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>


# 11696:80c30bd0c7d6 26-Oct-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF

the GPUISA class is meant to encapsulate any ISA-specific behavior - special
register accesses, isa-specific WF/kernel state, etc. - in a generic enough
way so that it may be used in ISA-agnostic code.

gpu-compute: use the GPUISA object to advance the PC

the GPU model treats the PC as a pointer to individual instruction objects -
which are store in a contiguous array - and not a byte address to be fetched
from the real memory system. this is ok for HSAIL because all instructions
are considered by the model to be the same size.

in machine ISA, however, instructions may be 32b or 64b, and branches are
calculated by advancing the PC by the number of words (4 byte chunks) it
needs to advance in the real instruction stream. because of this there is
a mismatch between the PC we use to index into the instruction array, and
the actual byte address PC the ISA expects. here we move the PC advance
calculation to the ISA so that differences in the instrucion sizes may be
accounted for in generic way.


# 11308:7d8836fd043d 19-Jan-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

gpu-compute: AMD's baseline GPU model


# 10935:acd48ddd725f 28-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

revert 5af8f40d8f2c


# 10934:5af8f40d8f2c 26-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

cpu: implements vector registers

This adds a vector register type. The type is defined as a std::array of a
fixed number of uint64_ts. The isa_parser.py has been modified to parse vector
register operands and generate the required code. Different cpus have vector
register files now.


# 10553:c1ad57c53a36 23-Nov-2014 Alexandru Dutu <alexandru.dutu@amd.com>

kvm, x86: Adding support for SE mode execution
This patch adds methods in KvmCPU model to handle KVM exits caused by syscall
instructions and page faults. These types of exits will be encountered if
KvmCPU is run in SE mode.


# 10319:4207f9bfcceb 03-Sep-2014 Andreas Sandberg <Andreas.Sandberg@ARM.com>

arch, cpu: Factor out the ExecContext into a proper base class

We currently generate and compile one version of the ISA code per CPU
model. This is obviously wasting a lot of resources at compile
time. This changeset factors out the interface into a separate
ExecContext class, which also serves as documentation for the
interface between CPUs and the ISA code. While doing so, this
changeset also fixes up interface inconsistencies between the
different CPU models.

The main argument for using one set of ISA code per CPU model has
always been performance as this avoid indirect branches in the
generated code. However, this argument does not hold water. Booting
Linux on a simulated ARM system running in atomic mode
(opt/10.linux-boot/realview-simple-atomic) is actually 2% faster
(compiled using clang 3.4) after applying this patch. Additionally,
compilation time is decreased by 35%.


# 10196:be0e1724eb39 09-May-2014 Curtis Dunham <Curtis.Dunham@arm.com>

arch: teach ISA parser how to split code across files

This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.

The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.

Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.

Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.

Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.


# 9920:028e4da64b42 15-Oct-2013 Yasuko Eckert <yasuko.eckert@amd.com>

cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.


# 9023:e9201a7bce59 26-May-2012 Gabe Black <gblack@eecs.umich.edu>

CPU: Merge the predecoder and decoder.

These classes are always used together, and merging them will give the ISAs
more flexibility in how they cache things and manage the process.


# 9020:14321ce30881 25-May-2012 Gabe Black <gblack@eecs.umich.edu>

Decode: Make the Decoder class defined per ISA.


# 8961:ff4762285f99 23-Apr-2012 Gabe Black <gblack@eecs.umich.edu>

ISA: Put parser generated files in a "generated" directory.

This is to avoid collision with non-generated files.


# 8887:20ea02da9c53 09-Mar-2012 Geoffrey Blake <geoffrey.blake@arm.com>

CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files. Also merges with the SE/FS changes.


# 8817:c36441eed919 07-Feb-2012 Gabe Black <gblack@eecs.umich.edu>

Faults: Turn off arch/faults.hh

Because there are no longer architecture independent but specialized functions
in arch/XXX/faults.hh, code that isn't using the faults from a particular ISA
no longer needs to be able to include them through the switching header file
arch/faults.hh. By removing that header file (arch/faults.hh), the potential
interface between ISA code and non ISA code is narrowed.


# 8585:e21224136182 24-Sep-2011 Gabe Black <gblack@eecs.umich.edu>

SCons: Add a comment I forgot to add in earlier.

This comment was supposed to be added to an earlier change as part of review
feedback, but I accidentally left it out when I pushed. Add it in now.


# 8584:26ece1659229 24-Sep-2011 Gabe Black <gblack@eecs.umich.edu>

SCons: Make the ISA parser a source for its output files like the comments say.

There was a change a while ago that refactored some scons stuff which got rid
of cpu_models.py but also accidentally got rid of the ISA parser as a source
for its target files. That meant that changes which affected the parser
wouldn't cause a rebuild unless they also changed one of the description
files. This change fixes that.


# 8335:9228e00459d4 02-Jun-2011 Nathan Binkert <nate@binkert.org>

scons: rename TraceFlags to DebugFlags


# 8105:906864dd0937 02-Mar-2011 Gabe Black <gblack@eecs.umich.edu>

Spelling: Fix the a spelling error by changing mmaped to mmapped.

There may not be a formally correct spelling for the past tense of mmap, but
mmapped is the spelling Google doesn't try to autocorrect. This makes sense
because it mirrors the past tense of map->mapped and not the past tense of
cape->caped.


# 7816:b5003ac75977 08-Jan-2011 Steve Reinhardt <steve.reinhardt@amd.com>

scons: show sources and targets when building, and colorize output.

I like the brevity of Ali's recent change, but the ambiguity of
sometimes showing the source and sometimes the target is a little
confusing. This patch makes scons typically list all sources and
all targets for each action, with the common path prefix factored
out for brevity. It's a little more verbose now but also more
informative.

Somehow Ali talked me into adding colors too, which is a whole
'nother story.


# 7799:5d0f62927d75 20-Dec-2010 Gabe Black <gblack@eecs.umich.edu>

Style: Replace some tabs with spaces.


# 7756:846fb3ffe0dc 15-Nov-2010 Ali Saidi <Ali.Saidi@ARM.com>

SCons: Cleanup SCons output during compile


# 7573:ef798deb9a02 22-Aug-2010 Gabe Black <gblack@eecs.umich.edu>

X86: Get rid of unused file arguments.hh.


# 6998:188393fbc381 10-Mar-2010 Nathan Binkert <nate@binkert.org>

scons: import ply to work around scons sys.path weirdness


# 6994:c6951099a1cb 26-Feb-2010 Nathan Binkert <nate@binkert.org>

cpu_models: get rid of cpu_models.py and move the stuff into SCons


# 6993:a24d88e850e2 26-Feb-2010 Nathan Binkert <nate@binkert.org>

isa_parser: Make SCons import the isa_parser
this is instead of forking a new interpreter


# 6329:5d8b91875859 09-Jul-2009 Gabe Black <gblack@eecs.umich.edu>

Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.


# 6313:95f69a436c82 09-Jul-2009 Gabe Black <gblack@eecs.umich.edu>

Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.


# 6179:83693f4b79fd 12-May-2009 Korey Sewell <ksewell@umich.edu>

inorder-alpha-port: initial inorder support of ALPHA
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)


# 5958:2d9737bf3c2f 27-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

Processes: Make getting and setting system call arguments part of a process object.


# 5944:60d926a40afd 25-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

ISA: Set up common trace flags for tracing registers.


# 5664:3b3756efad89 12-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

CPU: Create a microcode ROM object in the CPU which is defined by the ISA.


# 5228:b08c9c42907a 08-Nov-2007 Gabe Black <gblack@eecs.umich.edu>

ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs.


# 4781:59a75bd0ddf4 28-Jul-2007 Nathan Binkert <nate@binkert.org>

style: Check/Fix whitespace on SCons files


# 4240:cde9d7751cce 14-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

src/arch/mips/utility.hh:
src/arch/x86/SConscript:
Hand merge


# 4202:f7a05daec670 11-Mar-2007 Nathan Binkert <binkertn@umich.edu>

Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.


# 4182:5b2c0d266107 14-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.

src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
Make the predecoder an object with it's own switched header file.


# 3806:65ae5388c059 29-Nov-2006 Ali Saidi <saidi@eecs.umich.edu>

Add support for mmapped iprs to atomic cpu

src/arch/SConscript:
add mmaped_ipr.hh to switch headers
src/arch/sparc/asi.hh:
make ASI_IMPLICT=0 so by default nothing needs to be done
src/arch/sparc/miscregfile.hh:
miscregfile no longer needs to include asi.hh
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
implement panic instructions for mmaped ipr reads
src/cpu/simple/atomic.cc:
add check for mmaped iprs and handle them if it exists
src/mem/request.hh:
allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits


# 3565:6ad587fb7dfd 07-Nov-2006 Gabe Black <gblack@eecs.umich.edu>

Put kernel_stats back into arch.


# 3546:c4074658f1e1 07-Nov-2006 Gabe Black <gblack@eecs.umich.edu>

Made kern a switching header file directory.

SConstruct:
Put the code to make a switching header directory into a function so they are easy to make.
src/arch/SConscript:
Replace switching header code with the new function call.
src/kern/SConscript:
Created a new switching header directory in kern, and moved the declaration of some source files here.


# 3536:89aa06409e4d 06-Nov-2006 Gabe Black <gblack@eecs.umich.edu>

Remote GDB support has been changed to use inheritance. Alpha should work, but isn't tested. Other architectures will not.


# 3520:4f4a2054fd85 03-Nov-2006 Gabe Black <gblack@eecs.umich.edu>

Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the


# 3170:37fd1e73f836 08-Oct-2006 Steve Reinhardt <stever@eecs.umich.edu>

Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.

src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.


# 2984:797622d7b311 15-Aug-2006 Gabe Black <gblack@eecs.umich.edu>

Fixed ALPHA_FS by moving the remnants of isa_fullsys_traits.hh into arch/alpha/pagetable.hh and fixing up some includes


# 2972:f84c6c5309ce 11-Aug-2006 Gabe Black <gblack@eecs.umich.edu>

Pushed most of constants.hh back into isa_traits.hh and regfile.hh and created a seperate file for the syscallreturn class.


# 2921:e6bb350c3fa5 14-Jul-2006 Kevin Lim <ktlim@umich.edu>

Fix the CheckerCPU being included via python.

src/arch/SConscript:
Fixes for including the CheckerCPU if it's specified via command line. Previously the env variable was actually being modified.
src/cpu/SConscript:
Copy the CPU_MODELS from the env, don't create a proxy to it.


# 2766:0844a9607f77 17-Jun-2006 Kevin Lim <ktlim@umich.edu>

Fix up code to be able to use the Checker.

SConstruct:
Remove check for Checker from this SConstruct
src/arch/SConscript:
Specific check if CheckerCPU is being used. Not the cleanest, but works for now.
src/cpu/SConscript:
Code to handle using the CheckerCPU a little better. Allows -c to be used normally.


# 2718:4d3ca9c6a995 12-Jun-2006 Steve Reinhardt <stever@eecs.umich.edu>

Fix python binary name in arch/SConscript.
Also delete no-longer-needed SPARC test.py files (should
have gone with my last chnageset where LiveProcess
became ISA-independent).

src/arch/SConscript:
Mistakenly committed hard-coded python binary name.
Should use same python to run isa_parser that was
used to run scons.


# 2667:fe64b8353b1c 09-Jun-2006 Steve Reinhardt <stever@eecs.umich.edu>

Move main control from C++ into Python.
User script now invokes initialization and
simulation loop after building configuration.
These functions are exported from C++ to Python
using SWIG.

SConstruct:
Set up SWIG builder & scanner.
Set up symlinking of source files into build directory
(by not disabling the default behavior).
configs/test/test.py:
Rewrite to use new script-driven interface.
Include a sample option.
src/SConscript:
Set up symlinking of source files into build directory
(by not disabling the default behavior).
Add SWIG-generated main_wrap.cc to source list.
src/arch/SConscript:
Set up symlinking of source files into build directory
(by not disabling the default behavior).
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/trace/opt_cpu.cc:
src/cpu/trace/trace_cpu.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
src/sim/serialize.cc:
src/sim/syscall_emul.cc:
SimExit() is now exitSimLoop().
src/cpu/base.cc:
SimExitEvent is now SimLoopExitEvent
src/python/SConscript:
Add SWIG build command for main.i.
Use python/m5 in build dir as source for zip archive...
easy now with file duplication enabled.
src/python/m5/__init__.py:
- Move copyright notice back to C++ so we can print
it right away, even for interactive sessions.
- Get rid of argument parsing code; just provide default
option descriptors for user script to call optparse with.
- Don't clutter m5 namespace by sucking in all of m5.config
and m5.objects.
- Move instantiate() function here from config.py.
src/python/m5/config.py:
- Move instantiate() function to __init__.py.
- Param.Foo deferred type lookups must use m5.objects
namespace now (not m5).
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/AlphaFullCPU.py:
src/python/m5/objects/AlphaTLB.py:
src/python/m5/objects/BadDevice.py:
src/python/m5/objects/BaseCPU.py:
src/python/m5/objects/BaseCache.py:
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Bus.py:
src/python/m5/objects/CoherenceProtocol.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/IntrControl.py:
src/python/m5/objects/MemObject.py:
src/python/m5/objects/MemTest.py:
src/python/m5/objects/Pci.py:
src/python/m5/objects/PhysicalMemory.py:
src/python/m5/objects/Platform.py:
src/python/m5/objects/Process.py:
src/python/m5/objects/Repl.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/SimConsole.py:
src/python/m5/objects/SimpleDisk.py:
src/python/m5/objects/System.py:
src/python/m5/objects/Tsunami.py:
src/python/m5/objects/Uart.py:
Fix up imports (m5 namespace no longer includes m5.config).
src/sim/eventq.cc:
src/sim/eventq.hh:
Support for Python-called simulate() function:
- Use IsExitEvent flag to signal events that want
to exit the simulation loop gracefully (instead of
calling exit() to terminate the process).
- Modify interface to hand exit event object back to
caller so it can be inspected for cause.
src/sim/host.hh:
Add MaxTick constant.
src/sim/main.cc:
Move copyright notice back to C++ so we can print
it right away, even for interactive sessions.
Use PYTHONPATH environment var to set module path
(instead of clunky code injection method).
Move main control from here into Python:
- Separate initialization code and simulation loop
into separate functions callable from Python.
- Make Python interpreter invocation more pure (more
like directly invoking interpreter).
Add -i and -p flags (only options on binary itself;
other options processed by Python).
Import readline package when using interactive mode.
src/sim/sim_events.cc:
SimExitEvent is now SimLoopExitEvent, and uses
IsSimExit flag to terminate loop (instead of
exiting simulator process).
src/sim/sim_events.hh:
SimExitEvent is now SimLoopExitEvent, and uses
IsSimExit flag to terminate loop (instead of
exiting simulator process).
Get rid of a few unused constructors.
src/sim/sim_exit.hh:
SimExit() is now exitSimLoop().
Get rid of unused functions.
Add comments.


# 2665:a124942bacb8 31-May-2006 Ali Saidi <saidi@eecs.umich.edu>

Updated Authors from bk prs info


# 2637:18e4273315cd 22-May-2006 Steve Reinhardt <stever@eecs.umich.edu>

Get rid of FastCPU model.
It doesn't compile, and if we really want this we should
start over from scratch and see if we can reuse parts from
BaseSimpleCPU (e.g., derive a FastSimpleCPU).

SConstruct:
src/arch/SConscript:
src/cpu/cpu_models.py:
Get rid of FastCPU model.


# 2632:1bb2f91485ea 22-May-2006 Steve Reinhardt <stever@eecs.umich.edu>

New directory structure:
- simulator source now in 'src' subdirectory
- imported files from 'ext' repository
- support building in arbitrary places, including
outside of the source tree. See comment at top
of SConstruct file for more details.
Regression tests are temporarily disabled; that
syetem needs more extensive revisions.

SConstruct:
Update for new directory structure.
Modify to support build trees that are not subdirectories
of the source tree. See comment at top of file for
more details.
Regression tests are temporarily disabled.
src/arch/SConscript:
src/arch/isa_parser.py:
src/python/SConscript:
Update for new directory structure.