SConscript revision 9020:14321ce30881 
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Steve Reinhardt
30
31import sys
32import os
33
34Import('*')
35
36#################################################################
37#
38# ISA "switch header" generation.
39#
40# Auto-generate arch headers that include the right ISA-specific
41# header based on the setting of THE_ISA preprocessor variable.
42#
43#################################################################
44
45# List of headers to generate
46isa_switch_hdrs = Split('''
47        decoder.hh
48        interrupts.hh
49        isa.hh
50        isa_traits.hh
51        kernel_stats.hh
52        locked_mem.hh
53        microcode_rom.hh
54        mmapped_ipr.hh
55        mt.hh
56        process.hh
57        predecoder.hh
58        registers.hh
59        remote_gdb.hh
60        stacktrace.hh
61        tlb.hh
62        types.hh
63        utility.hh
64        vtophys.hh
65        ''')
66
67# Set up this directory to support switching headers
68make_switching_dir('arch', isa_switch_hdrs, env)
69
70#################################################################
71#
72# Include architecture-specific files.
73#
74#################################################################
75
76#
77# Build a SCons scanner for ISA files
78#
79import SCons.Scanner
80
81isa_scanner = SCons.Scanner.Classic("ISAScan",
82                                    [".isa", ".ISA"],
83                                    "SRCDIR",
84                                    r'^\s*##include\s+"([\w/.-]*)"')
85
86env.Append(SCANNERS = isa_scanner)
87
88#
89# Now create a Builder object that uses isa_parser.py to generate C++
90# output from the ISA description (*.isa) files.
91#
92
93isa_parser = File('isa_parser.py')
94
95# The emitter patches up the sources & targets to include the
96# autogenerated files as targets and isa parser itself as a source.
97def isa_desc_emitter(target, source, env):
98    cpu_models = list(env['CPU_MODELS'])
99    cpu_models.append('CheckerCPU')
100
101    # Several files are generated from the ISA description.
102    # We always get the basic decoder and header file.
103    target = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
104    # We also get an execute file for each selected CPU model.
105    target += [CpuModel.dict[cpu].filename for cpu in cpu_models]
106
107    # List the isa parser as a source.
108    source += [ isa_parser ]
109    # Add in the CPU models.
110    source += [ Value(m) for m in cpu_models ]
111
112    return [os.path.join("generated", t) for t in target], source
113
114ARCH_DIR = Dir('.')
115
116# import ply here because SCons screws with sys.path when performing actions.
117import ply
118
119def isa_desc_action_func(target, source, env):
120    # Add the current directory to the system path so we can import files
121    sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ]
122    import isa_parser
123
124    # Skip over the ISA description itself and the parser to the CPU models.
125    models = [ s.get_contents() for s in source[2:] ]
126    cpu_models = [CpuModel.dict[cpu] for cpu in models]
127    parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models)
128    parser.parse_isa_desc(source[0].abspath)
129isa_desc_action = MakeAction(isa_desc_action_func, Transform("ISA DESC", 1))
130
131# Also include the CheckerCPU as one of the models if it is being
132# enabled via command line.
133isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter)
134
135env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
136
137DebugFlag('IntRegs')
138DebugFlag('FloatRegs')
139DebugFlag('MiscRegs')
140CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])
141