SConscript revision 6994:c6951099a1cb
1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the 12# documentation and/or other materials provided with the distribution; 13# neither the name of the copyright holders nor the names of its 14# contributors may be used to endorse or promote products derived from 15# this software without specific prior written permission. 16# 17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28# 29# Authors: Steve Reinhardt 30 31import sys 32 33Import('*') 34 35################################################################# 36# 37# ISA "switch header" generation. 38# 39# Auto-generate arch headers that include the right ISA-specific 40# header based on the setting of THE_ISA preprocessor variable. 41# 42################################################################# 43 44# List of headers to generate 45isa_switch_hdrs = Split(''' 46 arguments.hh 47 faults.hh 48 interrupts.hh 49 isa.hh 50 isa_traits.hh 51 kernel_stats.hh 52 locked_mem.hh 53 microcode_rom.hh 54 mmaped_ipr.hh 55 mt.hh 56 process.hh 57 predecoder.hh 58 registers.hh 59 remote_gdb.hh 60 stacktrace.hh 61 tlb.hh 62 types.hh 63 utility.hh 64 vtophys.hh 65 ''') 66 67# Set up this directory to support switching headers 68make_switching_dir('arch', isa_switch_hdrs, env) 69 70################################################################# 71# 72# Include architecture-specific files. 73# 74################################################################# 75 76# 77# Build a SCons scanner for ISA files 78# 79import SCons.Scanner 80 81isa_scanner = SCons.Scanner.Classic("ISAScan", 82 [".isa", ".ISA"], 83 "SRCDIR", 84 r'^\s*##include\s+"([\w/.-]*)"') 85 86env.Append(SCANNERS = isa_scanner) 87 88# 89# Now create a Builder object that uses isa_parser.py to generate C++ 90# output from the ISA description (*.isa) files. 91# 92 93# The emitter patches up the sources & targets to include the 94# autogenerated files as targets and isa parser itself as a source. 95def isa_desc_emitter(target, source, env): 96 cpu_models = list(env['CPU_MODELS']) 97 if env['USE_CHECKER']: 98 cpu_models.append('CheckerCPU') 99 100 # Several files are generated from the ISA description. 101 # We always get the basic decoder and header file. 102 target = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ] 103 # We also get an execute file for each selected CPU model. 104 target += [CpuModel.dict[cpu].filename for cpu in cpu_models] 105 106 return target, source + [ Value(m) for m in cpu_models ] 107 108ARCH_DIR = Dir('.') 109 110def isa_desc_action(target, source, env): 111 # Add the current directory to the system path so we can import files 112 sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ] 113 import isa_parser 114 115 models = [ s.get_contents() for s in source[1:] ] 116 cpu_models = [CpuModel.dict[cpu] for cpu in models] 117 parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models) 118 parser.parse_isa_desc(source[0].abspath) 119 120# Also include the CheckerCPU as one of the models if it is being 121# enabled via command line. 122isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter) 123 124env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) 125 126TraceFlag('IntRegs') 127TraceFlag('FloatRegs') 128TraceFlag('MiscRegs') 129CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ]) 130