Searched hist:2007 (Results 826 - 850 of 895) sorted by relevance

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/gem5/src/base/stats/
H A Dtext.cc4209:57ff8c2ae0cf Mon Mar 12 14:13:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Get rid of those pesky valgrind warnings, Conditional jump or move depends on uninitialised value(s), in the stats package
4078:3f73f808bbd4 Sun Feb 18 01:52:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the Statistics and Statreset ParamContexts, and
expose all of the relevant functionality to python. Clean
up the mysql code while we're at it.
3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc
/gem5/src/sim/
H A Dsim_object.hh5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors.

SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
4076:e1c56b6b3072 Sun Feb 18 01:11:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Remove the event_ignore stuff since it was never really used
H A Dsim_object.cc5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors.

SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
4076:e1c56b6b3072 Sun Feb 18 01:11:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Remove the event_ignore stuff since it was never really used
H A Dstat_control.cc4078:3f73f808bbd4 Sun Feb 18 01:52:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the Statistics and Statreset ParamContexts, and
expose all of the relevant functionality to python. Clean
up the mysql code while we're at it.
H A Dpseudo_inst.cc5100:7a0180040755 Fri Sep 28 13:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Rename cycles() function to ticks()
4437:b6e304245729 Wed May 09 22:34:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> update for new reschedule semantics
4090:08bd6439b907 Wed Feb 21 21:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add pseduo instruction support for sparc

util/m5/Makefile.alpha:
Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
Make the makefile more reasonable
util/m5/Makefile.alpha:
Remove authors from copyright.
util/m5/Makefile.alpha:
Updated Authors from bk prs info
util/m5/Makefile.alpha:
bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
ivle and ivlb aren't used anymore
util/m5/m5op.h:
stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
move the op ids into their own header file since we can share them between sparc and alpha
4078:3f73f808bbd4 Sun Feb 18 01:52:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the Statistics and Statreset ParamContexts, and
expose all of the relevant functionality to python. Clean
up the mysql code while we're at it.
/gem5/src/arch/alpha/
H A Dev5.cc5004:7d94cedab264 Sun Aug 26 23:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: Make the page table more flexible.
The page table now stores actual page table entries. It is still a templated
class here, but this will be corrected in the near future.
4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
4395:9acb011a6c35 Sat Apr 21 19:11:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> fixes for solaris compile
4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
3923:a8ce86366fd3 Fri Jan 26 00:51:00 EST 2007 Lisa Hsu <hsul@eecs.umich.edu> eliminate cpu checkInterrupts bool, it is redundant and unnecessary.
H A Dprocess.cc5183:b4decf133fe4 Thu Oct 25 20:13:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> SE: Fix page table and system serialization, don't reinit process if this is a checkpoint restore.
5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack.
4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
H A Dprocess.hh5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack.
/gem5/src/cpu/o3/
H A Dcpu.hh5100:7a0180040755 Fri Sep 28 13:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Rename cycles() function to ticks()
4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
4988:5b26eba4283f Mon Aug 13 19:01:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Move the "translate" member functions back into the base o3 class.
4656:dbfa364feec8 Thu Jun 21 16:35:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro

src/cpu/o3/fetch_impl.hh:
hand merge
4636:afc8da9f526e Sat Apr 14 13:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
4632:be5b8f67b8fb Fri Apr 13 09:59:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
4598:56adf2e778a8 Wed Jun 20 11:15:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Don't do checker stuff if the checker is not defined
4329:52057dbec096 Wed Apr 04 15:38:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.

src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
4284:c8800319ed0c Fri Mar 23 13:20:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2

src/cpu/base_dyn_inst.hh:
Hand merge. Line is no longer needed because it's handled in the ISA.
4192:7accc6365bb9 Fri Mar 09 10:06:00 EST 2007 Kevin Lim <ktlim@umich.edu> Two fixes:
1. Make sure connectMemPorts() only gets called when the CPU's peer gets changed. This is done by making setPeer() virtual, and overriding it in the CPU's ports. When it gets called on a CPU's port (dcache specifically), it calls the normal setPeer() function, and also connectMemPorts().
2. Consolidate redundant code that handles switching in a CPU.

src/cpu/base.cc:
Move common code of switching over peers to base CPU.
src/cpu/base.hh:
Move common code of switching over peers to BaseCPU.
src/cpu/o3/cpu.cc:
Add in function that updates thread context's ports.
Also use updated function to takeOverFrom() in BaseCPU. This gets rid of some repeated code.
src/cpu/o3/cpu.hh:
Include function to update thread context's memory ports.
src/cpu/o3/lsq.hh:
Add function to dcache port that will update the memory ports upon getting a new peer.
Also include a function that will tell the CPU to update those memory ports.
src/cpu/o3/lsq_impl.hh:
Add function that will update the memory ports upon getting a new peer.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Add function that will update thread context's memory ports upon getting a new peer.
Also use the new BaseCPU's take over from function.
src/cpu/simple/atomic.hh:
Add in function (and dcache port) that will allow the dcache to update memory ports when it gets assigned a new peer.
src/cpu/simple/timing.hh:
Add function that will update thread context's memory ports upon getting a new peer.
src/mem/port.hh:
Make setPeer virtual so that other classes can override it.
H A Diew_impl.hh5215:68f719ce5496 Tue Nov 06 03:51:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> O3: Remove unneeded variable.
4636:afc8da9f526e Sat Apr 14 13:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
4632:be5b8f67b8fb Fri Apr 13 09:59:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
4329:52057dbec096 Wed Apr 04 15:38:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.

src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
4318:eb4241362a80 Mon Apr 02 13:55:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Remove/comment out DPRINTFs that were causing a segfault.

The removed ones were unnecessary. The commented out ones could be useful in the future, should this problem get fixed. See flyspray task #243.

src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
Remove/comment out DPRINTFs that were causing a segfault.
4033:7bb1223f9645 Fri Mar 23 11:40:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Handle status bits a little better, as well as non-speculative instructions.

src/cpu/o3/iew_impl.hh:
Allow for slightly more flexible handling of non-speculative instructions. They can be other classes now, such as loads or stores.

Also be sure to clear the state associated with squashes that are not used. i.e. if a squash due to a memory ordering violation happens on the same cycle as an older branch squashing, clear the state associated with the memory ordering violation.

Lastly don't consider uncached loads to officially be "at commit" until IEW receives the signal back from commit about the load.
src/cpu/o3/inst_queue_impl.hh:
Don't consider non-speculative instructions to be "at commit" until the IQ has received a signal from commit about the instruction. This prevents non-speculative instructions from being issued too early.
src/cpu/o3/mem_dep_unit_impl.hh:
Clear instruction's ability to issue if it's replayed.
3970:d54945bab95d Wed Jan 03 00:52:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
H A Dfetch.hh4653:19f884e6a48b Tue Jun 19 21:54:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into doughnut.hpl.hp.com:/home/gblack/newmem-o3-micro

src/cpu/base_dyn_inst_impl.hh:
src/cpu/o3/fetch_impl.hh:
Hand merge
4636:afc8da9f526e Sat Apr 14 13:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
4632:be5b8f67b8fb Fri Apr 13 09:59:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
4475:fb185cc1c845 Tue May 22 02:36:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Change getDeviceAddressRanges to use bool for snoop arg.
4329:52057dbec096 Wed Apr 04 15:38:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.

src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
4302:c45514c856b0 Thu Mar 29 00:02:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Update code so that the O3 CPU can handle not initially having anything hooked up to its ports. This fixes the segfault Ali recently found when using sampling.

src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
Update code so that the O3 CPU can handle not initially having anything hooked up to its ports.
4182:5b2c0d266107 Wed Mar 14 22:47:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.

src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
Make the predecoder an object with it's own switched header file.
H A Diew.hh5215:68f719ce5496 Tue Nov 06 03:51:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> O3: Remove unneeded variable.
4632:be5b8f67b8fb Fri Apr 13 09:59:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
4329:52057dbec096 Wed Apr 04 15:38:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.

src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
/gem5/src/cpu/
H A Dbase_dyn_inst.hh5177:4307a768e10e Mon Oct 22 17:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> CPU: Add functions to the "ExecContext"s that translate a given address.
5003:2eb7f972aabf Sun Aug 26 23:31:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> O3 CPU: Remove alignment check from dynamic instruction read/write functions.
4828:768d4cf6b0dc Tue Jul 31 20:34:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a flag to indicate an instruction triggers a syscall in SE mode.
4654:225cc048edfa Wed Jun 20 22:46:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix compiler errors.
4636:afc8da9f526e Sat Apr 14 13:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
4632:be5b8f67b8fb Fri Apr 13 09:59:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
4350:c3f402102507 Sat Apr 07 21:42:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Get the "hard" SPARC instructions working in o3. I don't like that the IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
4284:c8800319ed0c Fri Mar 23 13:20:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2

src/cpu/base_dyn_inst.hh:
Hand merge. Line is no longer needed because it's handled in the ISA.
4040:eb894f3fc168 Mon Feb 12 13:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> rename store conditional stuff as extra data so it can be used for conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic

src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
Make atomic memory ops atomic
Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
add a post access code block
src/arch/sparc/isa/includes.isa:
need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
add support for twinloads
add support for swap and conditional swap instructions
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
Add support for atomic swap memory commands
src/mem/packet_access.hh:
Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
Add support for atomic swap memory commands
Rename sc code to extradata
4032:8b987a6a2afc Fri Mar 23 11:33:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Two fixes:
1. Requests are handled more properly now. They assume the memory system takes control of the request upon sending out an access.
2. load-load ordering is maintained.

src/cpu/base_dyn_inst.hh:
Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out.

Also include some functions to allow certain status bits to be cleared.
src/cpu/base_dyn_inst_impl.hh:
Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out.
src/cpu/o3/fetch_impl.hh:
General correctness fixes. retryPkt is not necessarily always set, so handle it properly. Also consider the cache unblocked only when recvRetry is called.
src/cpu/o3/lsq_unit.hh:
Handle requests a little more correctly. Now that the requests aren't pointed to by the DynInst, be sure to delete the request if it's not being used by the memory system.

Also be sure to not store-load forward from an uncacheable store.
src/cpu/o3/lsq_unit_impl.hh:
Check to make sure load-load ordering was maintained.

Also handle requests a little more correctly.
/gem5/src/mem/
H A DSConscript5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
/gem5/tests/configs/
H A Dsimple-atomic.py4390:76bbcf725852 Sun Apr 22 14:39:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Update configs to set the CPU clock properly.
/gem5/system/alpha/console/
H A Dconsole.c8028:6b05deee0ca3 Fri Oct 19 16:44:00 EDT 2007 Geoffrey Blake <blakeg@umich.edu> Fix bug in MDT BITMAP to allow more than 2GB of memory.

Signed-off by Ali Saidi <saidi@eecs.umich.edu>
/gem5/src/arch/mips/isa/formats/
H A Dunknown.isa5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/src/base/
H A Dtime.cc3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc
H A Dremote_gdb.cc5105:511fe87ea24c Tue Oct 02 21:23:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Remote GDB: Get rid of an unwanted delete in SE.
4003:fe771fb5e3cf Tue Jan 30 02:45:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> sizeof with a pointer to dynamically allocated memory will return the size of the pointer, not the memory.
3980:9bcb2a2e9bb8 Sat Jan 27 01:59:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
Hand Merge
3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc
/gem5/configs/splash2/
H A Dcluster.py4876:a18cedc19da5 Sat Jun 30 20:59:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of remaining traces of obsolete CoherenceProtocol object.
/gem5/tests/
H A Drun.py4977:f167d9196a55 Tue Aug 14 00:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Regression: Use test-progs in /dist instead of tests/test-progs since they all aren't there.
/gem5/src/arch/mips/
H A Dprocess.cc5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
5183:b4decf133fe4 Thu Oct 25 20:13:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> SE: Fix page table and system serialization, don't reinit process if this is a checkpoint restore.
5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack.
/gem5/src/arch/alpha/linux/
H A Dsystem.hh4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
/gem5/src/mem/cache/prefetch/
H A DSConscript4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
/gem5/src/dev/
H A DDevice.py4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.

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