1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 *          Nathan Binkert
43 */
44
45/* @file
46 * User Console Definitions
47 */
48
49#ifndef __SIM_OBJECT_HH__
50#define __SIM_OBJECT_HH__
51
52#include <string>
53#include <vector>
54
55#include "base/stats/group.hh"
56#include "params/SimObject.hh"
57#include "sim/drain.hh"
58#include "sim/eventq.hh"
59#include "sim/eventq_impl.hh"
60#include "sim/port.hh"
61#include "sim/serialize.hh"
62
63class EventManager;
64class ProbeManager;
65
66/**
67 * Abstract superclass for simulation objects.  Represents things that
68 * correspond to physical components and can be specified via the
69 * config file (CPUs, caches, etc.).
70 *
71 * SimObject initialization is controlled by the instantiate method in
72 * src/python/m5/simulate.py. There are slightly different
73 * initialization paths when starting the simulation afresh and when
74 * loading from a checkpoint.  After instantiation and connecting
75 * ports, simulate.py initializes the object using the following call
76 * sequence:
77 *
78 * <ol>
79 * <li>SimObject::init()
80 * <li>SimObject::regStats()
81 * <li><ul>
82 *     <li>SimObject::initState() if starting afresh.
83 *     <li>SimObject::loadState() if restoring from a checkpoint.
84 *     </ul>
85 * <li>SimObject::resetStats()
86 * <li>SimObject::startup()
87 * <li>Drainable::drainResume() if resuming from a checkpoint.
88 * </ol>
89 *
90 * @note Whenever a method is called on all objects in the simulator's
91 * object tree (e.g., init(), startup(), or loadState()), a pre-order
92 * depth-first traversal is performed (see descendants() in
93 * SimObject.py). This has the effect of calling the method on the
94 * parent node <i>before</i> its children.
95 */
96class SimObject : public EventManager, public Serializable, public Drainable,
97                  public Stats::Group
98{
99  private:
100    typedef std::vector<SimObject *> SimObjectList;
101
102    /** List of all instantiated simulation objects. */
103    static SimObjectList simObjectList;
104
105    /** Manager coordinates hooking up probe points with listeners. */
106    ProbeManager *probeManager;
107
108  protected:
109    /** Cached copy of the object parameters. */
110    const SimObjectParams *_params;
111
112  public:
113    typedef SimObjectParams Params;
114    const Params *params() const { return _params; }
115    SimObject(const Params *_params);
116    virtual ~SimObject();
117
118  public:
119
120    virtual const std::string name() const { return params()->name; }
121
122    /**
123     * init() is called after all C++ SimObjects have been created and
124     * all ports are connected.  Initializations that are independent
125     * of unserialization but rely on a fully instantiated and
126     * connected SimObject graph should be done here.
127     */
128    virtual void init();
129
130    /**
131     * loadState() is called on each SimObject when restoring from a
132     * checkpoint.  The default implementation simply calls
133     * unserialize() if there is a corresponding section in the
134     * checkpoint.  However, objects can override loadState() to get
135     * other behaviors, e.g., doing other programmed initializations
136     * after unserialize(), or complaining if no checkpoint section is
137     * found.
138     *
139     * @param cp Checkpoint to restore the state from.
140     */
141    virtual void loadState(CheckpointIn &cp);
142
143    /**
144     * initState() is called on each SimObject when *not* restoring
145     * from a checkpoint.  This provides a hook for state
146     * initializations that are only required for a "cold start".
147     */
148    virtual void initState();
149
150    /**
151     * Register probe points for this object.
152     */
153    virtual void regProbePoints();
154
155    /**
156     * Register probe listeners for this object.
157     */
158    virtual void regProbeListeners();
159
160    /**
161     * Get the probe manager for this object.
162     */
163    ProbeManager *getProbeManager();
164
165    /**
166     * Get a port with a given name and index. This is used at binding time
167     * and returns a reference to a protocol-agnostic port.
168     *
169     * @param if_name Port name
170     * @param idx Index in the case of a VectorPort
171     *
172     * @return A reference to the given port
173     */
174    virtual Port &getPort(const std::string &if_name,
175                          PortID idx=InvalidPortID);
176
177    /**
178     * startup() is the final initialization call before simulation.
179     * All state is initialized (including unserialized state, if any,
180     * such as the curTick() value), so this is the appropriate place to
181     * schedule initial event(s) for objects that need them.
182     */
183    virtual void startup();
184
185    /**
186     * Provide a default implementation of the drain interface for
187     * objects that don't need draining.
188     */
189    DrainState drain() override { return DrainState::Drained; }
190
191    /**
192     * Write back dirty buffers to memory using functional writes.
193     *
194     * After returning, an object implementing this method should have
195     * written all its dirty data back to memory. This method is
196     * typically used to prepare a system with caches for
197     * checkpointing.
198     */
199    virtual void memWriteback() {};
200
201    /**
202     * Invalidate the contents of memory buffers.
203     *
204     * When the switching to hardware virtualized CPU models, we need
205     * to make sure that we don't have any cached state in the system
206     * that might become stale when we return. This method is used to
207     * flush all such state back to main memory.
208     *
209     * @warn This does <i>not</i> cause any dirty state to be written
210     * back to memory.
211     */
212    virtual void memInvalidate() {};
213
214    void serialize(CheckpointOut &cp) const override {};
215    void unserialize(CheckpointIn &cp) override {};
216
217    /**
218     * Serialize all SimObjects in the system.
219     */
220    static void serializeAll(CheckpointOut &cp);
221
222#ifdef DEBUG
223  public:
224    bool doDebugBreak;
225    static void debugObjectBreak(const std::string &objs);
226#endif
227
228    /**
229     * Find the SimObject with the given name and return a pointer to
230     * it.  Primarily used for interactive debugging.  Argument is
231     * char* rather than std::string to make it callable from gdb.
232     */
233    static SimObject *find(const char *name);
234};
235
236/**
237 * Base class to wrap object resolving functionality.
238 *
239 * This can be provided to the serialization framework to allow it to
240 * map object names onto C++ objects.
241 */
242class SimObjectResolver
243{
244  public:
245    virtual ~SimObjectResolver() { }
246
247    // Find a SimObject given a full path name
248    virtual SimObject *resolveSimObject(const std::string &name) = 0;
249};
250
251#ifdef DEBUG
252void debugObjectBreak(const char *objs);
253#endif
254
255#endif // __SIM_OBJECT_HH__
256