12SN/A/*
21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
37534Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
42SN/A * All rights reserved.
52SN/A *
62SN/A * Redistribution and use in source and binary forms, with or without
72SN/A * modification, are permitted provided that the following conditions are
82SN/A * met: redistributions of source code must retain the above copyright
92SN/A * notice, this list of conditions and the following disclaimer;
102SN/A * redistributions in binary form must reproduce the above copyright
112SN/A * notice, this list of conditions and the following disclaimer in the
122SN/A * documentation and/or other materials provided with the distribution;
132SN/A * neither the name of the copyright holders nor the names of its
142SN/A * contributors may be used to endorse or promote products derived from
152SN/A * this software without specific prior written permission.
162SN/A *
172SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu *
292665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
302665Ssaidi@eecs.umich.edu *          Nathan Binkert
312SN/A */
322SN/A
3311793Sbrandon.potter@amd.com#include "sim/sim_object.hh"
3411793Sbrandon.potter@amd.com
3512334Sgabeblack@google.com#include "base/logging.hh"
361031SN/A#include "base/match.hh"
37330SN/A#include "base/trace.hh"
388320Ssteve.reinhardt@amd.com#include "debug/Checkpoint.hh"
3910023Smatt.horsnell@ARM.com#include "sim/probe/probe.hh"
402SN/A
412SN/Ausing namespace std;
422SN/A
432SN/A
442SN/A////////////////////////////////////////////////////////////////////////
452SN/A//
462SN/A// SimObject member definitions
472SN/A//
482SN/A////////////////////////////////////////////////////////////////////////
492SN/A
502SN/A//
512SN/A// static list of all SimObjects, used for initialization etc.
522SN/A//
532SN/ASimObject::SimObjectList SimObject::simObjectList;
542SN/A
552SN/A//
562SN/A// SimObject constructor: used to maintain static simObjectList
572SN/A//
584762Snate@binkert.orgSimObject::SimObject(const Params *p)
5914205Sandreas.sandberg@arm.com    : EventManager(getEventQueue(p->eventq_index)),
6014205Sandreas.sandberg@arm.com      Stats::Group(nullptr),
6114205Sandreas.sandberg@arm.com      _params(p)
622SN/A{
631031SN/A#ifdef DEBUG
641031SN/A    doDebugBreak = false;
651031SN/A#endif
661553SN/A    simObjectList.push_back(this);
6710023Smatt.horsnell@ARM.com    probeManager = new ProbeManager(this);
681553SN/A}
691553SN/A
7010422Sandreas.hansson@arm.comSimObject::~SimObject()
7110422Sandreas.hansson@arm.com{
7210422Sandreas.hansson@arm.com    delete probeManager;
7310422Sandreas.hansson@arm.com}
7410422Sandreas.hansson@arm.com
75465SN/Avoid
76465SN/ASimObject::init()
77465SN/A{
78465SN/A}
79465SN/A
807492Ssteve.reinhardt@amd.comvoid
8110905Sandreas.sandberg@arm.comSimObject::loadState(CheckpointIn &cp)
827532Ssteve.reinhardt@amd.com{
8310905Sandreas.sandberg@arm.com    if (cp.sectionExists(name())) {
848320Ssteve.reinhardt@amd.com        DPRINTF(Checkpoint, "unserializing\n");
8510905Sandreas.sandberg@arm.com        // This works despite name() returning a fully qualified name
8610905Sandreas.sandberg@arm.com        // since we are at the top level.
8710905Sandreas.sandberg@arm.com        unserializeSection(cp, name());
888320Ssteve.reinhardt@amd.com    } else {
898320Ssteve.reinhardt@amd.com        DPRINTF(Checkpoint, "no checkpoint section found\n");
908320Ssteve.reinhardt@amd.com    }
917532Ssteve.reinhardt@amd.com}
927532Ssteve.reinhardt@amd.com
937532Ssteve.reinhardt@amd.comvoid
947532Ssteve.reinhardt@amd.comSimObject::initState()
957532Ssteve.reinhardt@amd.com{
967532Ssteve.reinhardt@amd.com}
977532Ssteve.reinhardt@amd.com
987532Ssteve.reinhardt@amd.comvoid
997492Ssteve.reinhardt@amd.comSimObject::startup()
1007492Ssteve.reinhardt@amd.com{
1017492Ssteve.reinhardt@amd.com}
1027492Ssteve.reinhardt@amd.com
10310023Smatt.horsnell@ARM.com/**
10410023Smatt.horsnell@ARM.com * No probe points by default, so do nothing in base.
10510023Smatt.horsnell@ARM.com */
10610023Smatt.horsnell@ARM.comvoid
10710023Smatt.horsnell@ARM.comSimObject::regProbePoints()
10810023Smatt.horsnell@ARM.com{
10910023Smatt.horsnell@ARM.com}
11010023Smatt.horsnell@ARM.com
11110023Smatt.horsnell@ARM.com/**
11210023Smatt.horsnell@ARM.com * No probe listeners by default, so do nothing in base.
11310023Smatt.horsnell@ARM.com */
11410023Smatt.horsnell@ARM.comvoid
11510023Smatt.horsnell@ARM.comSimObject::regProbeListeners()
11610023Smatt.horsnell@ARM.com{
11710023Smatt.horsnell@ARM.com}
11810023Smatt.horsnell@ARM.com
11910023Smatt.horsnell@ARM.comProbeManager *
12010023Smatt.horsnell@ARM.comSimObject::getProbeManager()
12110023Smatt.horsnell@ARM.com{
12210023Smatt.horsnell@ARM.com    return probeManager;
12310023Smatt.horsnell@ARM.com}
12410023Smatt.horsnell@ARM.com
12513781Sgabeblack@google.comPort &
12613781Sgabeblack@google.comSimObject::getPort(const std::string &if_name, PortID idx)
12713781Sgabeblack@google.com{
12813781Sgabeblack@google.com    fatal("%s does not have any port named %s\n", name(), if_name);
12913781Sgabeblack@google.com}
13013781Sgabeblack@google.com
1312SN/A//
132395SN/A// static function: serialize all SimObjects.
133395SN/A//
134395SN/Avoid
13510905Sandreas.sandberg@arm.comSimObject::serializeAll(CheckpointOut &cp)
136395SN/A{
137573SN/A    SimObjectList::reverse_iterator ri = simObjectList.rbegin();
138573SN/A    SimObjectList::reverse_iterator rend = simObjectList.rend();
139395SN/A
140573SN/A    for (; ri != rend; ++ri) {
141573SN/A        SimObject *obj = *ri;
14210905Sandreas.sandberg@arm.com        // This works despite name() returning a fully qualified name
14310905Sandreas.sandberg@arm.com        // since we are at the top level.
14411240Sandreas.sandberg@arm.com        obj->serializeSection(cp, obj->name());
145395SN/A   }
146395SN/A}
147843SN/A
1487492Ssteve.reinhardt@amd.com
1491031SN/A#ifdef DEBUG
1501031SN/A//
1511031SN/A// static function: flag which objects should have the debugger break
1521031SN/A//
1531031SN/Avoid
1541031SN/ASimObject::debugObjectBreak(const string &objs)
1551031SN/A{
1561031SN/A    SimObjectList::const_iterator i = simObjectList.begin();
1571031SN/A    SimObjectList::const_iterator end = simObjectList.end();
1581031SN/A
1591031SN/A    ObjectMatch match(objs);
1601031SN/A    for (; i != end; ++i) {
1611031SN/A        SimObject *obj = *i;
1621031SN/A        obj->doDebugBreak = match.match(obj->name());
1631031SN/A   }
1641031SN/A}
1651031SN/A
1661031SN/Avoid
1671031SN/AdebugObjectBreak(const char *objs)
1681031SN/A{
1691031SN/A    SimObject::debugObjectBreak(string(objs));
1701031SN/A}
1711031SN/A#endif
1721031SN/A
1735314Sstever@gmail.comSimObject *
1745314Sstever@gmail.comSimObject::find(const char *name)
1755314Sstever@gmail.com{
1765314Sstever@gmail.com    SimObjectList::const_iterator i = simObjectList.begin();
1775314Sstever@gmail.com    SimObjectList::const_iterator end = simObjectList.end();
1785314Sstever@gmail.com
1795314Sstever@gmail.com    for (; i != end; ++i) {
1805314Sstever@gmail.com        SimObject *obj = *i;
1815314Sstever@gmail.com        if (obj->name() == name)
1825314Sstever@gmail.com            return obj;
1835314Sstever@gmail.com    }
1845314Sstever@gmail.com
1855314Sstever@gmail.com    return NULL;
1865314Sstever@gmail.com}
187