Searched defs:master (Results 1 - 25 of 28) sorted by relevance

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/gem5/src/arch/generic/
H A DBaseTLB.py40 master = MasterPort("Port closer to memory side") variable in class:BaseTLB
/gem5/src/mem/qos/
H A Dpolicy.hh115 Policy::pair(M master, T value) argument
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H A Dpolicy_fixed_prio.cc62 FixedPriorityPolicy::initMasterName(std::string master, uint8_t priority) argument
69 FixedPriorityPolicy::initMasterObj(const SimObject* master, uint8_t priority) argument
H A Dmem_ctrl.cc323 const std::string master = _system->getMasterName(i); local
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H A Dpolicy_pf.cc58 PropFairPolicy::initMaster(const Master master, const double score) argument
73 PropFairPolicy::initMasterName(const std::string master, const double score) argument
79 PropFairPolicy::initMasterObj(const SimObject* master, const double score) argument
/gem5/src/mem/ruby/network/
H A DMessageBuffer.py45 master = MasterPort("Master port to MessageBuffer receiver") variable in class:MessageBuffer
H A DNetwork.py56 master = VectorMasterPort("CPU master port") variable in class:RubyNetwork
/gem5/src/mem/
H A DBridge.py49 master = MasterPort('Master port') variable in class:Bridge
H A DAddrMapper.py53 master = MasterPort("Master port") variable in class:AddrMapper
H A DMemChecker.py51 master = MasterPort("Master port") variable in class:MemCheckerMonitor
H A DSerialLink.py54 master = MasterPort('Master port') variable in class:SerialLink
H A DMemDelay.py46 master = MasterPort("Master port") variable in class:MemDelay
H A DCommMonitor.py53 master = MasterPort("Master port") variable in class:CommMonitor
H A DXBar.py55 master = VectorMasterPort("Vector port for connecting slaves") variable in class:BaseXBar
H A Dnoncoherent_xbar.cc265 auto master = masterPorts[master_port_id]; local
/gem5/system/alpha/console/
H A Ddbmentry.S97 master: label
/gem5/src/sim/probe/
H A Dmem.hh60 MasterID master; member in struct:ProbePoints::PacketInfo
/gem5/src/systemc/tests/systemc/kernel/process_control/test04/
H A Dtest04.cpp82 void master() function
/gem5/ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/
H A Dtlm_req_rsp_channels.h95 tlm_master_imp< REQ , RSP > master; member in class:tlm::tlm_req_rsp_channel
/gem5/src/systemc/ext/tlm_core/1/req_rsp/channels/req_rsp_channels/
H A Dreq_rsp_channels.hh87 tlm_master_imp<REQ, RSP> master; member in class:tlm::tlm_req_rsp_channel
/gem5/src/gpu-compute/
H A DX86GPUTLB.py64 master = VectorMasterPort("Port on side closer to memory") variable in class:X86GPUTLB
75 master = VectorMasterPort("Port on side closer to memory") variable in class:TLBCoalescer
/gem5/src/mem/ruby/system/
H A DSequencer.py41 master = VectorMasterPort("CPU master port") variable in class:RubyPort
/gem5/ext/sst/
H A Dgem5.cc256 auto master = new ExtMaster(this, info, owner, s); local
/gem5/src/dev/net/
H A Ddist_iface.hh515 static DistIface *master; member in class:DistIface
/gem5/src/dev/storage/
H A Dide_ctrl.hh96 IdeDisk *master, *slave; member in struct:IdeController::Channel

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