xref: /gem5/src/arch/generic/BaseTLB.py

# Copyright (c) 2008 The Hewlett-Packard Development Company
# Copyright (c) 2018 Metempsy Technology Consulting
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# Authors: Gabe Black
#          Ivan Pizarro

from m5.params import *
from m5.SimObject import SimObject

class BaseTLB(SimObject):
    type = 'BaseTLB'
    abstract = True
    cxx_header = "arch/generic/tlb.hh"
    # Ports to connect with other TLB levels
    slave  = VectorSlavePort("Port closer to the CPU side")
    master = MasterPort("Port closer to memory side")