112966SMatteo.Andreozzi@arm.com/* 213430SMatteo.Andreozzi@arm.com * Copyright (c) 2017-2018 ARM Limited 312966SMatteo.Andreozzi@arm.com * All rights reserved 412966SMatteo.Andreozzi@arm.com * 512966SMatteo.Andreozzi@arm.com * The license below extends only to copyright in the software and shall 612966SMatteo.Andreozzi@arm.com * not be construed as granting a license to any other intellectual 712966SMatteo.Andreozzi@arm.com * property including but not limited to intellectual property relating 812966SMatteo.Andreozzi@arm.com * to a hardware implementation of the functionality of the software 912966SMatteo.Andreozzi@arm.com * licensed hereunder. You may use the software subject to the license 1012966SMatteo.Andreozzi@arm.com * terms below provided that you ensure that this notice is replicated 1112966SMatteo.Andreozzi@arm.com * unmodified and in its entirety in all distributions of the software, 1212966SMatteo.Andreozzi@arm.com * modified or unmodified, in source code or in binary form. 1312966SMatteo.Andreozzi@arm.com * 1412966SMatteo.Andreozzi@arm.com * Redistribution and use in source and binary forms, with or without 1512966SMatteo.Andreozzi@arm.com * modification, are permitted provided that the following conditions are 1612966SMatteo.Andreozzi@arm.com * met: redistributions of source code must retain the above copyright 1712966SMatteo.Andreozzi@arm.com * notice, this list of conditions and the following disclaimer; 1812966SMatteo.Andreozzi@arm.com * redistributions in binary form must reproduce the above copyright 1912966SMatteo.Andreozzi@arm.com * notice, this list of conditions and the following disclaimer in the 2012966SMatteo.Andreozzi@arm.com * documentation and/or other materials provided with the distribution; 2112966SMatteo.Andreozzi@arm.com * neither the name of the copyright holders nor the names of its 2212966SMatteo.Andreozzi@arm.com * contributors may be used to endorse or promote products derived from 2312966SMatteo.Andreozzi@arm.com * this software without specific prior written permission. 2412966SMatteo.Andreozzi@arm.com * 2512966SMatteo.Andreozzi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612966SMatteo.Andreozzi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712966SMatteo.Andreozzi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812966SMatteo.Andreozzi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912966SMatteo.Andreozzi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012966SMatteo.Andreozzi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112966SMatteo.Andreozzi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212966SMatteo.Andreozzi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312966SMatteo.Andreozzi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412966SMatteo.Andreozzi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512966SMatteo.Andreozzi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612966SMatteo.Andreozzi@arm.com * 3712966SMatteo.Andreozzi@arm.com * Authors: Matteo Andreozzi 3812966SMatteo.Andreozzi@arm.com */ 3912966SMatteo.Andreozzi@arm.com 4012966SMatteo.Andreozzi@arm.com#include "mem_ctrl.hh" 4112966SMatteo.Andreozzi@arm.com 4212966SMatteo.Andreozzi@arm.com#include "turnaround_policy.hh" 4312966SMatteo.Andreozzi@arm.com 4412966SMatteo.Andreozzi@arm.comnamespace QoS { 4512966SMatteo.Andreozzi@arm.com 4612966SMatteo.Andreozzi@arm.comMemCtrl::MemCtrl(const QoSMemCtrlParams * p) 4712966SMatteo.Andreozzi@arm.com : AbstractMemory(p), 4812966SMatteo.Andreozzi@arm.com policy(p->qos_policy), 4912966SMatteo.Andreozzi@arm.com turnPolicy(p->qos_turnaround_policy), 5012966SMatteo.Andreozzi@arm.com queuePolicy(QueuePolicy::create(p)), 5112966SMatteo.Andreozzi@arm.com _numPriorities(p->qos_priorities), 5212966SMatteo.Andreozzi@arm.com qosPriorityEscalation(p->qos_priority_escalation), 5312966SMatteo.Andreozzi@arm.com qosSyncroScheduler(p->qos_syncro_scheduler), 5412966SMatteo.Andreozzi@arm.com totalReadQueueSize(0), totalWriteQueueSize(0), 5512966SMatteo.Andreozzi@arm.com busState(READ), busStateNext(READ) 5612966SMatteo.Andreozzi@arm.com{ 5712966SMatteo.Andreozzi@arm.com // Set the priority policy 5812966SMatteo.Andreozzi@arm.com if (policy) { 5912966SMatteo.Andreozzi@arm.com policy->setMemCtrl(this); 6012966SMatteo.Andreozzi@arm.com } 6112966SMatteo.Andreozzi@arm.com 6212966SMatteo.Andreozzi@arm.com // Set the queue priority policy 6312966SMatteo.Andreozzi@arm.com if (queuePolicy) { 6412966SMatteo.Andreozzi@arm.com queuePolicy->setMemCtrl(this); 6512966SMatteo.Andreozzi@arm.com } 6612966SMatteo.Andreozzi@arm.com 6712966SMatteo.Andreozzi@arm.com // Set the bus turnaround policy 6812966SMatteo.Andreozzi@arm.com if (turnPolicy) { 6912966SMatteo.Andreozzi@arm.com turnPolicy->setMemCtrl(this); 7012966SMatteo.Andreozzi@arm.com } 7112966SMatteo.Andreozzi@arm.com 7212966SMatteo.Andreozzi@arm.com readQueueSizes.resize(_numPriorities); 7312966SMatteo.Andreozzi@arm.com writeQueueSizes.resize(_numPriorities); 7412966SMatteo.Andreozzi@arm.com serviceTick.resize(_numPriorities); 7512966SMatteo.Andreozzi@arm.com} 7612966SMatteo.Andreozzi@arm.com 7712966SMatteo.Andreozzi@arm.comMemCtrl::~MemCtrl() 7812966SMatteo.Andreozzi@arm.com{} 7912966SMatteo.Andreozzi@arm.com 8012966SMatteo.Andreozzi@arm.comvoid 8112966SMatteo.Andreozzi@arm.comMemCtrl::init() 8212966SMatteo.Andreozzi@arm.com{ 8312966SMatteo.Andreozzi@arm.com AbstractMemory::init(); 8412966SMatteo.Andreozzi@arm.com} 8512966SMatteo.Andreozzi@arm.com 8612966SMatteo.Andreozzi@arm.comvoid 8712966SMatteo.Andreozzi@arm.comMemCtrl::logRequest(BusState dir, MasterID m_id, uint8_t qos, 8812966SMatteo.Andreozzi@arm.com Addr addr, uint64_t entries) 8912966SMatteo.Andreozzi@arm.com{ 9012966SMatteo.Andreozzi@arm.com // If needed, initialize all counters and statistics 9112966SMatteo.Andreozzi@arm.com // for this master 9212966SMatteo.Andreozzi@arm.com addMaster(m_id); 9312966SMatteo.Andreozzi@arm.com 9412966SMatteo.Andreozzi@arm.com DPRINTF(QOS, 9512966SMatteo.Andreozzi@arm.com "QoSMemCtrl::logRequest MASTER %s [id %d] address %d" 9612966SMatteo.Andreozzi@arm.com " prio %d this master q packets %d" 9712966SMatteo.Andreozzi@arm.com " - queue size %d - requested entries %d\n", 9812966SMatteo.Andreozzi@arm.com masters[m_id], m_id, addr, qos, packetPriorities[m_id][qos], 9912966SMatteo.Andreozzi@arm.com (dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos], 10012966SMatteo.Andreozzi@arm.com entries); 10112966SMatteo.Andreozzi@arm.com 10212966SMatteo.Andreozzi@arm.com if (dir == READ) { 10312966SMatteo.Andreozzi@arm.com readQueueSizes[qos] += entries; 10412966SMatteo.Andreozzi@arm.com totalReadQueueSize += entries; 10512966SMatteo.Andreozzi@arm.com } else if (dir == WRITE) { 10612966SMatteo.Andreozzi@arm.com writeQueueSizes[qos] += entries; 10712966SMatteo.Andreozzi@arm.com totalWriteQueueSize += entries; 10812966SMatteo.Andreozzi@arm.com } 10912966SMatteo.Andreozzi@arm.com 11012966SMatteo.Andreozzi@arm.com packetPriorities[m_id][qos] += entries; 11112966SMatteo.Andreozzi@arm.com for (auto j = 0; j < entries; ++j) { 11212966SMatteo.Andreozzi@arm.com requestTimes[m_id][addr].push_back(curTick()); 11312966SMatteo.Andreozzi@arm.com } 11412966SMatteo.Andreozzi@arm.com 11512966SMatteo.Andreozzi@arm.com // Record statistics 11612966SMatteo.Andreozzi@arm.com avgPriority[m_id].sample(qos); 11712966SMatteo.Andreozzi@arm.com 11812966SMatteo.Andreozzi@arm.com // Compute avg priority distance 11912966SMatteo.Andreozzi@arm.com 12012966SMatteo.Andreozzi@arm.com for (uint8_t i = 0; i < packetPriorities[m_id].size(); ++i) { 12112966SMatteo.Andreozzi@arm.com uint8_t distance = 12212966SMatteo.Andreozzi@arm.com (abs(int(qos) - int(i))) * packetPriorities[m_id][i]; 12312966SMatteo.Andreozzi@arm.com 12412966SMatteo.Andreozzi@arm.com if (distance > 0) { 12512966SMatteo.Andreozzi@arm.com avgPriorityDistance[m_id].sample(distance); 12612966SMatteo.Andreozzi@arm.com DPRINTF(QOS, 12712966SMatteo.Andreozzi@arm.com "QoSMemCtrl::logRequest MASTER %s [id %d]" 12812966SMatteo.Andreozzi@arm.com " registering priority distance %d for priority %d" 12912966SMatteo.Andreozzi@arm.com " (packets %d)\n", 13012966SMatteo.Andreozzi@arm.com masters[m_id], m_id, distance, i, 13112966SMatteo.Andreozzi@arm.com packetPriorities[m_id][i]); 13212966SMatteo.Andreozzi@arm.com } 13312966SMatteo.Andreozzi@arm.com } 13412966SMatteo.Andreozzi@arm.com 13512966SMatteo.Andreozzi@arm.com DPRINTF(QOS, 13612966SMatteo.Andreozzi@arm.com "QoSMemCtrl::logRequest MASTER %s [id %d] prio %d " 13712966SMatteo.Andreozzi@arm.com "this master q packets %d - new queue size %d\n", 13812966SMatteo.Andreozzi@arm.com masters[m_id], m_id, qos, packetPriorities[m_id][qos], 13912966SMatteo.Andreozzi@arm.com (dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos]); 14012966SMatteo.Andreozzi@arm.com 14112966SMatteo.Andreozzi@arm.com} 14212966SMatteo.Andreozzi@arm.com 14312966SMatteo.Andreozzi@arm.comvoid 14412966SMatteo.Andreozzi@arm.comMemCtrl::logResponse(BusState dir, MasterID m_id, uint8_t qos, 14512966SMatteo.Andreozzi@arm.com Addr addr, uint64_t entries, double delay) 14612966SMatteo.Andreozzi@arm.com{ 14712966SMatteo.Andreozzi@arm.com panic_if(!hasMaster(m_id), 14812966SMatteo.Andreozzi@arm.com "Logging response with invalid master\n"); 14912966SMatteo.Andreozzi@arm.com 15012966SMatteo.Andreozzi@arm.com DPRINTF(QOS, 15112966SMatteo.Andreozzi@arm.com "QoSMemCtrl::logResponse MASTER %s [id %d] address %d prio" 15212966SMatteo.Andreozzi@arm.com " %d this master q packets %d" 15312966SMatteo.Andreozzi@arm.com " - queue size %d - requested entries %d\n", 15412966SMatteo.Andreozzi@arm.com masters[m_id], m_id, addr, qos, packetPriorities[m_id][qos], 15512966SMatteo.Andreozzi@arm.com (dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos], 15612966SMatteo.Andreozzi@arm.com entries); 15712966SMatteo.Andreozzi@arm.com 15812966SMatteo.Andreozzi@arm.com if (dir == READ) { 15912966SMatteo.Andreozzi@arm.com readQueueSizes[qos] -= entries; 16012966SMatteo.Andreozzi@arm.com totalReadQueueSize -= entries; 16112966SMatteo.Andreozzi@arm.com } else if (dir == WRITE) { 16212966SMatteo.Andreozzi@arm.com writeQueueSizes[qos] -= entries; 16312966SMatteo.Andreozzi@arm.com totalWriteQueueSize -= entries; 16412966SMatteo.Andreozzi@arm.com } 16512966SMatteo.Andreozzi@arm.com 16612966SMatteo.Andreozzi@arm.com panic_if(packetPriorities[m_id][qos] == 0, 16712966SMatteo.Andreozzi@arm.com "QoSMemCtrl::logResponse master %s negative packets for priority" 16812966SMatteo.Andreozzi@arm.com " %d", masters[m_id], qos); 16912966SMatteo.Andreozzi@arm.com 17012966SMatteo.Andreozzi@arm.com packetPriorities[m_id][qos] -= entries; 17112966SMatteo.Andreozzi@arm.com 17212966SMatteo.Andreozzi@arm.com for (auto j = 0; j < entries; ++j) { 17312966SMatteo.Andreozzi@arm.com auto it = requestTimes[m_id].find(addr); 17412966SMatteo.Andreozzi@arm.com panic_if(it == requestTimes[m_id].end(), 17512966SMatteo.Andreozzi@arm.com "QoSMemCtrl::logResponse master %s unmatched response for" 17612966SMatteo.Andreozzi@arm.com " address %d received", masters[m_id], addr); 17712966SMatteo.Andreozzi@arm.com 17812966SMatteo.Andreozzi@arm.com // Load request time 17912966SMatteo.Andreozzi@arm.com uint64_t requestTime = it->second.front(); 18012966SMatteo.Andreozzi@arm.com 18112966SMatteo.Andreozzi@arm.com // Remove request entry 18212966SMatteo.Andreozzi@arm.com it->second.pop_front(); 18312966SMatteo.Andreozzi@arm.com 18412966SMatteo.Andreozzi@arm.com // Remove whole address entry if last one 18512966SMatteo.Andreozzi@arm.com if (it->second.empty()) { 18612966SMatteo.Andreozzi@arm.com requestTimes[m_id].erase(it); 18712966SMatteo.Andreozzi@arm.com } 18812966SMatteo.Andreozzi@arm.com // Compute latency 18912966SMatteo.Andreozzi@arm.com double latency = (double) (curTick() + delay - requestTime) 19012966SMatteo.Andreozzi@arm.com / SimClock::Float::s; 19112966SMatteo.Andreozzi@arm.com 19212966SMatteo.Andreozzi@arm.com if (latency > 0) { 19312966SMatteo.Andreozzi@arm.com // Record per-priority latency stats 19412966SMatteo.Andreozzi@arm.com if (priorityMaxLatency[qos].value() < latency) { 19512966SMatteo.Andreozzi@arm.com priorityMaxLatency[qos] = latency; 19612966SMatteo.Andreozzi@arm.com } 19712966SMatteo.Andreozzi@arm.com 19812966SMatteo.Andreozzi@arm.com if (priorityMinLatency[qos].value() > latency 19912966SMatteo.Andreozzi@arm.com || priorityMinLatency[qos].value() == 0) { 20012966SMatteo.Andreozzi@arm.com priorityMinLatency[qos] = latency; 20112966SMatteo.Andreozzi@arm.com } 20212966SMatteo.Andreozzi@arm.com } 20312966SMatteo.Andreozzi@arm.com } 20412966SMatteo.Andreozzi@arm.com 20512966SMatteo.Andreozzi@arm.com DPRINTF(QOS, 20612966SMatteo.Andreozzi@arm.com "QoSMemCtrl::logResponse MASTER %s [id %d] prio %d " 20712966SMatteo.Andreozzi@arm.com "this master q packets %d - new queue size %d\n", 20812966SMatteo.Andreozzi@arm.com masters[m_id], m_id, qos, packetPriorities[m_id][qos], 20912966SMatteo.Andreozzi@arm.com (dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos]); 21012966SMatteo.Andreozzi@arm.com} 21112966SMatteo.Andreozzi@arm.com 21212966SMatteo.Andreozzi@arm.comuint8_t 21312966SMatteo.Andreozzi@arm.comMemCtrl::schedule(MasterID m_id, uint64_t data) 21412966SMatteo.Andreozzi@arm.com{ 21512966SMatteo.Andreozzi@arm.com if (policy) { 21612966SMatteo.Andreozzi@arm.com return policy->schedule(m_id, data); 21712966SMatteo.Andreozzi@arm.com } else { 21812966SMatteo.Andreozzi@arm.com DPRINTF(QOS, 21912966SMatteo.Andreozzi@arm.com "QoSScheduler::schedule master ID [%d] " 22012966SMatteo.Andreozzi@arm.com "data received [%d], but QoS scheduler not initialized\n", 22112966SMatteo.Andreozzi@arm.com m_id,data); 22212966SMatteo.Andreozzi@arm.com return 0; 22312966SMatteo.Andreozzi@arm.com } 22412966SMatteo.Andreozzi@arm.com} 22512966SMatteo.Andreozzi@arm.com 22612966SMatteo.Andreozzi@arm.comuint8_t 22712966SMatteo.Andreozzi@arm.comMemCtrl::schedule(const PacketPtr pkt) 22812966SMatteo.Andreozzi@arm.com{ 22912966SMatteo.Andreozzi@arm.com assert(pkt->req); 23012966SMatteo.Andreozzi@arm.com 23112966SMatteo.Andreozzi@arm.com if (policy) { 23212966SMatteo.Andreozzi@arm.com return schedule(pkt->req->masterId(), pkt->getSize()); 23312966SMatteo.Andreozzi@arm.com } else { 23412966SMatteo.Andreozzi@arm.com DPRINTF(QOS, "QoSScheduler::schedule Packet received [Qv %d], " 23512966SMatteo.Andreozzi@arm.com "but QoS scheduler not initialized\n", 23612966SMatteo.Andreozzi@arm.com pkt->qosValue()); 23712966SMatteo.Andreozzi@arm.com return pkt->qosValue(); 23812966SMatteo.Andreozzi@arm.com } 23912966SMatteo.Andreozzi@arm.com} 24012966SMatteo.Andreozzi@arm.com 24112966SMatteo.Andreozzi@arm.comMemCtrl::BusState 24212966SMatteo.Andreozzi@arm.comMemCtrl::selectNextBusState() 24312966SMatteo.Andreozzi@arm.com{ 24412966SMatteo.Andreozzi@arm.com auto bus_state = getBusState(); 24512966SMatteo.Andreozzi@arm.com 24612966SMatteo.Andreozzi@arm.com if (turnPolicy) { 24712966SMatteo.Andreozzi@arm.com DPRINTF(QOS, 24812966SMatteo.Andreozzi@arm.com "QoSMemoryTurnaround::selectBusState running policy %s\n", 24912966SMatteo.Andreozzi@arm.com turnPolicy->name()); 25012966SMatteo.Andreozzi@arm.com 25112966SMatteo.Andreozzi@arm.com bus_state = turnPolicy->selectBusState(); 25212966SMatteo.Andreozzi@arm.com } else { 25312966SMatteo.Andreozzi@arm.com DPRINTF(QOS, 25412966SMatteo.Andreozzi@arm.com "QoSMemoryTurnaround::selectBusState running " 25512966SMatteo.Andreozzi@arm.com "default bus direction selection policy\n"); 25612966SMatteo.Andreozzi@arm.com 25712966SMatteo.Andreozzi@arm.com if ((!getTotalReadQueueSize() && bus_state == MemCtrl::READ) || 25812966SMatteo.Andreozzi@arm.com (!getTotalWriteQueueSize() && bus_state == MemCtrl::WRITE)) { 25912966SMatteo.Andreozzi@arm.com // READ/WRITE turnaround 26012966SMatteo.Andreozzi@arm.com bus_state = (bus_state == MemCtrl::READ) ? MemCtrl::WRITE : 26112966SMatteo.Andreozzi@arm.com MemCtrl::READ; 26212966SMatteo.Andreozzi@arm.com 26312966SMatteo.Andreozzi@arm.com } 26412966SMatteo.Andreozzi@arm.com } 26512966SMatteo.Andreozzi@arm.com 26612966SMatteo.Andreozzi@arm.com return bus_state; 26712966SMatteo.Andreozzi@arm.com} 26812966SMatteo.Andreozzi@arm.com 26912966SMatteo.Andreozzi@arm.comvoid 27012966SMatteo.Andreozzi@arm.comMemCtrl::addMaster(MasterID m_id) 27112966SMatteo.Andreozzi@arm.com{ 27212966SMatteo.Andreozzi@arm.com if (!hasMaster(m_id)) { 27312966SMatteo.Andreozzi@arm.com masters.emplace(m_id, _system->getMasterName(m_id)); 27412966SMatteo.Andreozzi@arm.com packetPriorities[m_id].resize(numPriorities(), 0); 27512966SMatteo.Andreozzi@arm.com 27612966SMatteo.Andreozzi@arm.com DPRINTF(QOS, 27712966SMatteo.Andreozzi@arm.com "QoSMemCtrl::addMaster registering" 27812966SMatteo.Andreozzi@arm.com " Master %s [id %d]\n", 27912966SMatteo.Andreozzi@arm.com masters[m_id], m_id); 28012966SMatteo.Andreozzi@arm.com } 28112966SMatteo.Andreozzi@arm.com} 28212966SMatteo.Andreozzi@arm.com 28312966SMatteo.Andreozzi@arm.comvoid 28412966SMatteo.Andreozzi@arm.comMemCtrl::regStats() 28512966SMatteo.Andreozzi@arm.com{ 28612966SMatteo.Andreozzi@arm.com AbstractMemory::regStats(); 28712966SMatteo.Andreozzi@arm.com 28812966SMatteo.Andreozzi@arm.com using namespace Stats; 28912966SMatteo.Andreozzi@arm.com 29012966SMatteo.Andreozzi@arm.com // Initializes per master statistics 29112966SMatteo.Andreozzi@arm.com avgPriority.init(_system->maxMasters()).name(name() + ".avgPriority") 29212966SMatteo.Andreozzi@arm.com .desc("Average QoS priority value for accepted requests") 29312966SMatteo.Andreozzi@arm.com .flags(nozero | nonan).precision(2); 29412966SMatteo.Andreozzi@arm.com 29512966SMatteo.Andreozzi@arm.com avgPriorityDistance.init(_system->maxMasters()) 29612966SMatteo.Andreozzi@arm.com .name(name() + ".avgPriorityDistance") 29712966SMatteo.Andreozzi@arm.com .desc("Average QoS priority distance between assigned and " 29812966SMatteo.Andreozzi@arm.com "queued values").flags(nozero | nonan); 29912966SMatteo.Andreozzi@arm.com 30012966SMatteo.Andreozzi@arm.com priorityMinLatency.init(numPriorities()) 30112966SMatteo.Andreozzi@arm.com .name(name() + ".priorityMinLatency") 30212966SMatteo.Andreozzi@arm.com .desc("per QoS priority minimum request to response latency (s)") 30312966SMatteo.Andreozzi@arm.com .precision(12); 30412966SMatteo.Andreozzi@arm.com 30512966SMatteo.Andreozzi@arm.com priorityMaxLatency.init(numPriorities()) 30612966SMatteo.Andreozzi@arm.com .name(name() + ".priorityMaxLatency") 30712966SMatteo.Andreozzi@arm.com .desc("per QoS priority maximum request to response latency (s)") 30812966SMatteo.Andreozzi@arm.com .precision(12); 30912966SMatteo.Andreozzi@arm.com 31012966SMatteo.Andreozzi@arm.com numReadWriteTurnArounds.name(name() + ".numReadWriteTurnArounds") 31112966SMatteo.Andreozzi@arm.com .desc("Number of turnarounds from READ to WRITE"); 31212966SMatteo.Andreozzi@arm.com 31312966SMatteo.Andreozzi@arm.com numWriteReadTurnArounds.name(name() + ".numWriteReadTurnArounds") 31412966SMatteo.Andreozzi@arm.com .desc("Number of turnarounds from WRITE to READ"); 31512966SMatteo.Andreozzi@arm.com 31612966SMatteo.Andreozzi@arm.com numStayReadState.name(name() + ".numStayReadState") 31712966SMatteo.Andreozzi@arm.com .desc("Number of times bus staying in READ state"); 31812966SMatteo.Andreozzi@arm.com 31912966SMatteo.Andreozzi@arm.com numStayWriteState.name(name() + ".numStayWriteState") 32012966SMatteo.Andreozzi@arm.com .desc("Number of times bus staying in WRITE state"); 32112966SMatteo.Andreozzi@arm.com 32212966SMatteo.Andreozzi@arm.com for (int i = 0; i < _system->maxMasters(); i++) { 32312966SMatteo.Andreozzi@arm.com const std::string master = _system->getMasterName(i); 32412966SMatteo.Andreozzi@arm.com avgPriority.subname(i, master); 32512966SMatteo.Andreozzi@arm.com avgPriorityDistance.subname(i, master); 32612966SMatteo.Andreozzi@arm.com } 32712966SMatteo.Andreozzi@arm.com 32812966SMatteo.Andreozzi@arm.com for (int j = 0; j < numPriorities(); ++j) { 32912966SMatteo.Andreozzi@arm.com priorityMinLatency.subname(j, std::to_string(j)); 33012966SMatteo.Andreozzi@arm.com priorityMaxLatency.subname(j, std::to_string(j)); 33112966SMatteo.Andreozzi@arm.com } 33212966SMatteo.Andreozzi@arm.com} 33312966SMatteo.Andreozzi@arm.com 33412966SMatteo.Andreozzi@arm.comvoid 33512966SMatteo.Andreozzi@arm.comMemCtrl::recordTurnaroundStats() 33612966SMatteo.Andreozzi@arm.com{ 33712966SMatteo.Andreozzi@arm.com if (busStateNext != busState) { 33812966SMatteo.Andreozzi@arm.com if (busState == READ) { 33912966SMatteo.Andreozzi@arm.com numWriteReadTurnArounds++; 34012966SMatteo.Andreozzi@arm.com } else if (busState == WRITE) { 34112966SMatteo.Andreozzi@arm.com numReadWriteTurnArounds++; 34212966SMatteo.Andreozzi@arm.com } 34312966SMatteo.Andreozzi@arm.com } else { 34412966SMatteo.Andreozzi@arm.com if (busState == READ) { 34512966SMatteo.Andreozzi@arm.com numStayReadState++; 34612966SMatteo.Andreozzi@arm.com } else if (busState == WRITE) { 34712966SMatteo.Andreozzi@arm.com numStayWriteState++; 34812966SMatteo.Andreozzi@arm.com } 34912966SMatteo.Andreozzi@arm.com } 35012966SMatteo.Andreozzi@arm.com} 35112966SMatteo.Andreozzi@arm.com 35212966SMatteo.Andreozzi@arm.com} // namespace QoS 353