Searched refs:op2 (Results 1 - 25 of 30) sorted by relevance

12

/gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/int_datatype/
H A Dint_datatype.cpp73 unsigned int op2 = VAL2; local
79 r1 = op1 * op2; // Multiplication
81 r2 = op1 / op2; // Division
83 r3 = op1 % op2; // Modulus
85 r4 = op1 + op2; // Addition
87 r5 = op1 - op2; // Subtraction
91 r7 = op1 && op2; // Logical AND
93 r8 = op1 || op2; // Logical OR
95 r9 = op1 < op2; // Less than
97 r10 = op1 <= op2; // Les
[all...]
/gem5/src/arch/arm/insts/
H A Dfplib.hh79 T fplibAdd(T op1, T op2, FPSCR &fpscr);
82 int fplibCompare(T op1, T op2, bool signal_nans, FPSCR &fpscr);
85 bool fplibCompareEQ(T op1, T op2, FPSCR &fpscr);
88 bool fplibCompareGE(T op1, T op2, FPSCR &fpscr);
91 bool fplibCompareGT(T op1, T op2, FPSCR &fpscr);
94 bool fplibCompareUN(T op1, T op2, FPSCR &fpscr);
100 T fplibDiv(T op1, T op2, FPSCR &fpscr);
106 T fplibMax(T op1, T op2, FPSCR &fpscr);
109 T fplibMaxNum(T op1, T op2, FPSCR &fpscr);
112 T fplibMin(T op1, T op2, FPSC
[all...]
H A Dvfp.cc56 printIntReg(ss, op2);
73 printIntReg(ss, op2);
121 printFloatReg(ss, op2);
136 printFloatReg(ss, op2);
149 printFloatReg(ss, op2);
164 printFloatReg(ss, op2);
251 fixDest(bool flush, bool defaultNan, fpType val, fpType op1, fpType op2) argument
259 const bool nan2 = std::isnan(op2);
261 const bool signal2 = nan2 && ((fpToBits(op2) & qnan) != qnan);
267 val = bitsToFp(fpToBits(op2) | qna
292 fixDivDest(bool flush, bool defaultNan, fpType val, fpType op1, fpType op2) argument
951 ternaryOp(FPSCR &fpscr, fpType op1, fpType op2, fpType op3, fpType (*func)(fpType, fpType, fpType), bool flush, bool defaultNan, uint32_t rMode) const argument
1029 binaryOp(FPSCR &fpscr, fpType op1, fpType op2, fpType (*func)(fpType, fpType), bool flush, bool defaultNan, uint32_t rMode) const argument
1170 nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2) argument
[all...]
H A Ddata64.hh83 IntRegIndex dest, op1, op2; member in class:ArmISA::DataXSRegOp
91 dest(_dest), op1(_op1), op2(_op2),
102 IntRegIndex dest, op1, op2; member in class:ArmISA::DataXERegOp
110 dest(_dest), op1(_op1), op2(_op2),
168 IntRegIndex dest, op1, op2; member in class:ArmISA::DataX2RegOp
173 dest(_dest), op1(_op1), op2(_op2)
183 IntRegIndex dest, op1, op2; member in class:ArmISA::DataX2RegImmOp
190 dest(_dest), op1(_op1), op2(_op2), imm(_imm)
200 IntRegIndex dest, op1, op2, op3; member in class:ArmISA::DataX3RegOp
206 dest(_dest), op1(_op1), op2(_op
235 IntRegIndex op1, op2; member in class:ArmISA::DataXCondCompRegOp
253 IntRegIndex dest, op1, op2; member in class:ArmISA::DataXCondSelOp
[all...]
H A Dsve.hh77 IntRegIndex op2; member in class:ArmISA::SveIndexIROp
83 dest(_dest), imm1(_imm1), op2(_op2)
107 IntRegIndex op2; member in class:ArmISA::SveIndexRROp
113 dest(_dest), op1(_op1), op2(_op2)
155 IntRegIndex dest, op1, op2; member in class:ArmISA::SveWhileOp
162 dest(_dest), op1(_op1), op2(_op2), srcIs32b(_srcIs32b)
170 IntRegIndex op1, op2; member in class:ArmISA::SveCompTermOp
175 op1(_op1), op2(_op2)
293 IntRegIndex dest, op2, gp; member in class:ArmISA::SveBinDestrPredOp
299 dest(_dest), op2(_op
308 IntRegIndex dest, op1, op2, gp; member in class:ArmISA::SveBinConstrPredOp
325 IntRegIndex dest, op1, op2; member in class:ArmISA::SveBinUnpredOp
339 IntRegIndex dest, op1, op2; member in class:ArmISA::SveBinIdxUnpredOp
355 IntRegIndex dest, op1, op2, gp; member in class:ArmISA::SvePredLogicalOp
371 IntRegIndex dest, op1, op2; member in class:ArmISA::SvePredBinPermOp
386 IntRegIndex dest, gp, op1, op2; member in class:ArmISA::SveCmpOp
417 IntRegIndex dest, op1, op2, gp; member in class:ArmISA::SveTerPredOp
432 IntRegIndex dest, op2; member in class:ArmISA::SveTerImmUnpredOp
492 IntRegIndex op1, op2; member in class:ArmISA::SveIntCmpOp
532 IntRegIndex dest, op1, op2; member in class:ArmISA::SveAdrOp
589 IntRegIndex op2; member in class:ArmISA::SvePartBrkPropOp
645 IntRegIndex op2; member in class:ArmISA::SveTblOp
785 IntRegIndex dest, op1, op2; member in class:ArmISA::SveDotProdIdxOp
803 IntRegIndex dest, op1, op2; member in class:ArmISA::SveDotProdOp
820 IntRegIndex dest, op1, op2, gp; member in class:ArmISA::SveComplexOp
837 IntRegIndex dest, op1, op2; member in class:ArmISA::SveComplexIdxOp
[all...]
H A Dfplib.cc2379 fplibAdd(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
2382 uint16_t result = fp16_add(op1, op2, 0, modeConv(fpscr), &flags);
2389 fplibAdd(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
2392 uint32_t result = fp32_add(op1, op2, 0, modeConv(fpscr), &flags);
2399 fplibAdd(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
2402 uint64_t result = fp64_add(op1, op2, 0, modeConv(fpscr), &flags);
2409 fplibCompare(uint16_t op1, uint16_t op2, bool signal_nans, FPSCR &fpscr) argument
2417 fp16_unpack(&sgn2, &exp2, &mnt2, op2, mode, &flags);
2425 if (op1 == op2 || (!mnt1 && !mnt2)) {
2443 fplibCompare(uint32_t op1, uint32_t op2, boo argument
2477 fplibCompare(uint64_t op1, uint64_t op2, bool signal_nans, FPSCR &fpscr) argument
2864 fplibMulAdd(uint16_t addend, uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
2874 fplibMulAdd(uint32_t addend, uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
2884 fplibMulAdd(uint64_t addend, uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
2894 fplibDiv(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
2904 fplibDiv(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
2914 fplibDiv(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
3131 fp16_minmaxnum(uint16_t *op1, uint16_t *op2, int sgn) argument
3143 fp32_minmaxnum(uint32_t *op1, uint32_t *op2, int sgn) argument
3155 fp64_minmaxnum(uint64_t *op1, uint64_t *op2, int sgn) argument
3168 fplibMax(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
3191 fplibMax(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
3214 fplibMax(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
3237 fplibMaxNum(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
3245 fplibMaxNum(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
3253 fplibMaxNum(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
3261 fplibMin(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
3284 fplibMin(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
3307 fplibMin(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
3330 fplibMinNum(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
3338 fplibMinNum(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
3346 fplibMinNum(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
3354 fplibMul(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
3364 fplibMul(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
3374 fplibMul(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
3384 fplibMulX(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
3415 fplibMulX(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
3446 fplibMulX(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
3622 fplibRSqrtStepFused(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
3652 fplibRSqrtStepFused(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
3682 fplibRSqrtStepFused(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
3898 fplibRecipStepFused(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
3928 fplibRecipStepFused(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
3958 fplibRecipStepFused(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
4388 fplibTrigMulAdd(uint8_t coeff_index, uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
4422 fplibTrigMulAdd(uint8_t coeff_index, uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
4456 fplibTrigSMul(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
4476 fplibTrigSMul(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
4495 fplibTrigSMul(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
4514 fplibTrigSSel(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument
4525 fplibTrigSSel(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument
4536 fplibTrigSSel(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument
[all...]
H A Ddata64.cc69 op2, INTREG_ZERO, shiftAmt, shiftType, 0);
78 op2, INTREG_ZERO, shiftAmt, LSL, 0);
126 printIntReg(ss, op2);
139 printIntReg(ss, op2);
153 printIntReg(ss, op2);
180 printIntReg(ss, op2);
197 printIntReg(ss, op2);
H A Dvfp.hh131 flushToZero(fpType &op1, fpType &op2) argument
134 bool flush2 = flushToZero(op2);
149 vfpFlushToZero(FPSCR &fpscr, fpType &op1, fpType &op2) argument
152 vfpFlushToZero(fpscr, op2);
222 fpType fixDest(FPSCR fpscr, fpType val, fpType op1, fpType op2);
225 fpType fixDivDest(FPSCR fpscr, fpType val, fpType op1, fpType op2);
471 void nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2);
589 fpMulAdd(T op1, T op2, T addend) argument
594 result = fmaf(op1, op2, addend);
596 result = fma(op1, op2, adden
885 IntRegIndex op1, op2; member in class:ArmISA::FpCondCompRegOp
903 IntRegIndex dest, op1, op2; member in class:ArmISA::FpCondSelOp
977 IntRegIndex op2; member in class:ArmISA::FpRegRegRegOp
996 IntRegIndex op2; member in class:ArmISA::FpRegRegRegCondOp
1018 IntRegIndex op2; member in class:ArmISA::FpRegRegRegRegOp
1039 IntRegIndex op2; member in class:ArmISA::FpRegRegRegImmOp
[all...]
H A Dbranch.cc71 printIntReg(ss, op2);
H A Dbranch.hh112 IntRegIndex op2; member in class:ArmISA::BranchRegReg
117 PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2)
H A Dsve.cc110 printIntReg(ss, op2);
135 printIntReg(ss, op2);
153 printIntReg(ss, op2, opWidth);
164 printIntReg(ss, op2);
274 printVecReg(ss, op2, true);
293 printVecReg(ss, op2, true);
306 printVecReg(ss, op2, true);
320 printVecReg(ss, op2, true);
342 printVecPredReg(ss, op2);
355 printVecPredReg(ss, op2);
[all...]
H A Dpred_inst.cc92 op2, INTREG_ZERO, shiftAmt, shiftType, 0);
101 op2, shift, 0, shiftType, 0);
H A Dmisc.hh123 IntRegIndex op2; member in class:McrrOp
130 PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2),
204 IntRegIndex op2; member in class:RegRegRegImmOp
211 dest(_dest), op1(_op1), op2(_op2), imm(_imm)
223 IntRegIndex op2; member in class:RegRegRegRegOp
230 dest(_dest), op1(_op1), op2(_op2), op3(_op3)
242 IntRegIndex op2; member in class:RegRegRegOp
247 dest(_dest), op1(_op1), op2(_op2)
H A Dstatic_inst.hh82 saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false) argument
84 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
115 uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false) argument
117 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
H A Dpred_inst.hh300 IntRegIndex dest, op1, op2; member in class:ArmISA::DataRegOp
308 dest(_dest), op1(_op1), op2(_op2),
319 IntRegIndex dest, op1, op2, shift; member in class:ArmISA::DataRegRegOp
326 dest(_dest), op1(_op1), op2(_op2), shift(_shift),
H A Dmisc.cc169 printIntReg(ss, op2);
212 printIntReg(ss, op2);
226 printIntReg(ss, op2);
241 printIntReg(ss, op2);
H A Dmisc64.hh84 IntRegIndex op2; member in class:RegRegRegImmOp64
91 dest(_dest), op1(_op1), op2(_op2), imm(_imm)
/gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/std_ulogic_vector_datatype/
H A Dstd_ulogic_vector_datatype.cpp492 std_ulogic_vector<4> op2; local
493 op2 = VAL2;
503 // r1 = op1 * op2; // Multiplication
505 // r2 = op1 / op2; // Division
507 // r3 = op1 % op2; // Modulus
509 // r4 = op1 + op2; // Addition
511 // r5 = op1 - op2; // Subtraction
515 // r7 = op1 && op2; // Logical AND
517 // r8 = op1 || op2; // Logical OR
519 // r9 = op1 < op2; // Les
[all...]
/gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/std_ulogic_datatype/
H A Dstd_ulogic_datatype.cpp197 std_ulogic op2 = sc_logic(VAL2); local
203 // r1 = op1 * op2; // Multiplication
205 // r2 = op1 / op2; // Division
207 // r3 = op1 % op2; // Modulus
209 // r4 = op1 + op2; // Addition
211 // r5 = op1 - op2; // Subtraction
215 // r7 = op1 && op2; // Logical AND
217 // r8 = op1 || op2; // Logical OR
219 // r9 = op1 < op2; // Less than
221 // r10 = op1 <= op2; // Les
[all...]
/gem5/src/arch/arm/
H A Dmiscregs.cc611 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
630 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
1202 unsigned op2)
1212 switch (op2) {
1218 switch (op2) {
1224 switch (op2) {
1232 switch (op2) {
1244 switch (op2) {
1250 switch (op2) {
1260 switch (op2) {
1200 decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2) argument
[all...]
H A Dutility.hh309 uint32_t crm, uint32_t op2, IntRegIndex rt)
316 (op2 << 17) |
308 msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, IntRegIndex rt) argument
/gem5/src/base/
H A Dcircular_queue.hh105 moduloAdd(uint32_t op1, uint32_t op2, uint32_t size) argument
107 return (op1 + op2) % size;
112 moduloSub(uint32_t op1, uint32_t op2, uint32_t size) argument
114 int32_t ret = sub(op1, op2, size);
119 sub(uint32_t op1, uint32_t op2, uint32_t size) argument
121 if (op1 > op2)
122 return (op1 - op2) % size;
124 return -((op2 - op1) % size);
/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc188 const uint64_t op2(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP2));
190 decodeAArch64SysReg(op0, op1, crn, crm, op2));
192 inform(" %s (op0: %i, op1: %i, crn: %i, crm: %i, op2: %i): %s",
193 miscRegName[idx], op0, op1, crn, crm, op2,
378 const uint64_t op2(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP2));
379 const MiscRegIndex idx(decodeAArch64SysReg(op0, op1, crn, crm, op2));
/gem5/ext/systemc/src/sysc/datatypes/fx/
H A Dsc_fix.h1055 #define DEFN_BIN_OP_T(op,op2,tp1,tp2) \
1068 c.set_bit( i, a.get_bit( i ) op2 b.get_bit( i ) ); \
1089 #define DEFN_BIN_FNC_T(fnc,op2,tp1,tp2) \
1098 c.set_bit( i, a.get_bit( i ) op2 b.get_bit( i ) ); \
1178 #define DEFN_ASN_OP_T(op,op2,tp) \
1187 set_bit( i, get_bit( i ) op2 b.get_bit( i ) ); \
1769 #define DEFN_BIN_OP_T(op,op2,tp1,tp2) \
1782 c.set_bit( i, a.get_bit( i ) op2 b.get_bit( i ) ); \
1795 #define DEFN_BIN_FNC_T(fnc,op2,tp1,tp2) \
1804 c.set_bit( i, a.get_bit( i ) op2
[all...]
H A Dsc_ufix.h1058 #define DEFN_BIN_OP_T(op,op2,tp1,tp2) \
1071 c.set_bit( i, a.get_bit( i ) op2 b.get_bit( i ) ); \
1092 #define DEFN_BIN_FNC_T(fnc,op2,tp1,tp2) \
1101 c.set_bit( i, a.get_bit( i ) op2 b.get_bit( i ) ); \
1181 #define DEFN_ASN_OP_T(op,op2,tp) \
1190 set_bit( i, get_bit( i ) op2 b.get_bit( i ) ); \
1772 #define DEFN_BIN_OP_T(op,op2,tp1,tp2) \
1785 c.set_bit( i, a.get_bit( i ) op2 b.get_bit( i ) ); \
1798 #define DEFN_BIN_FNC_T(fnc,op2,tp1,tp2) \
1807 c.set_bit( i, a.get_bit( i ) op2
[all...]

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