| /gem5/src/cpu/simple/ |
| H A D | AtomicSimpleCPU.py | 65 def addSimPointProbe(self, interval):
67 simpoint.interval = interval
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| /gem5/tests/configs/ |
| H A D | realview64-simple-atomic-checkpoint.py | 49 run_test = functools.partial(checkpoint.run_test, interval=1.0)
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| H A D | checkpoint.py | 60 def _run_step(name, restore=None, interval=0.5):
63 checkpoitn name) the system and run for interval seconds of
64 simulated time. At the end of the simulation interval, create a
77 e = m5.simulate(m5.ticks.fromSeconds(interval))
88 def run_test(root, interval=0.5, max_checkpoints=5):
106 "interval" : interval,
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| /gem5/src/cpu/simple/probes/ |
| H A D | SimPoint.py | 47 interval = Param.UInt64(100000000, "Interval Size (insts)") variable in class:SimPoint
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| H A D | simpoint.cc | 47 intervalSize(p->interval),
113 // Reached end of interval if the sum of the current inst count
115 // interval (intervalDrift) is greater than/equal to the interval size.
117 // summarize interval and display BBV info
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| /gem5/util/ |
| H A D | checkpoint-tester.py | 34 # Given an M5 command and an interval (in ticks), this script will:
35 # 1. Run the command, dumping periodic checkpoints at the given interval.
73 parser.add_option('-i', '--interval', type='int')
78 interval = options.interval variable
96 initial_args = ['--take-checkpoints', '%d,%d' % (interval, interval)]
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| /gem5/src/cpu/testers/memtest/ |
| H A D | MemTest.py | 52 interval = Param.Cycles(1, "Interval between request packets") variable in class:MemTest
65 "Progress report interval (in accesses)")
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| H A D | memtest.cc | 94 interval(p->interval),
301 schedule(tickEvent, clockEdge(interval));
336 schedule(tickEvent, clockEdge(interval));
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| H A D | memtest.hh | 127 const Cycles interval; member in class:MemTest
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| /gem5/src/dev/ |
| H A D | intel_8254_timer.cc | 279 interval = (Tick)(SimClock::Float::s / 1193180.0);
306 clocks * interval);
307 counter->parent->schedule(this, curTick() + clocks * interval);
315 return (when() - curTick() + interval - 1) / interval;
327 return interval;
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| H A D | mc146818.hh | 54 Tick interval; member in struct:MC146818::RTCEvent
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| H A D | mc146818.cc | 313 : parent(_parent), interval(i), offset(i)
321 parent->schedule(this, curTick() + interval);
328 parent->schedule(this, curTick() + interval);
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| H A D | intel_8254_timer.hh | 89 Tick interval; member in class:Intel8254Timer::Counter::CounterEvent
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| /gem5/src/dev/serial/ |
| H A D | uart8250.cc | 79 static const Tick interval = 225 * SimClock::Int::ns; local
81 event->name(), curTick() + interval);
83 schedule(event, curTick() + interval);
85 reschedule(event, curTick() + interval);
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| /gem5/configs/common/ |
| H A D | Simulation.py | 186 print("#%d, start_inst:%d, weight:%f, interval:%d, warmup:%d" %
297 print("interval length:", interval_length)
303 # Simpoint analysis output starts interval counts with 0.
316 interval = int(m.group(1))
329 if (interval * interval_length - warmup_length > 0):
331 interval * interval_length - warmup_length
337 actual_warmup_length = interval * interval_length
339 simpoints.append((interval, weight, starting_inst_count,
345 interval, weight, starting_inst_count, actual_warmup_length = s
346 print(str(interval), st
[all...] |
| /gem5/src/cpu/ |
| H A D | base.hh | 101 void interval(Tick ival) { _interval = ival; } function in class:CPUProgressEvent
102 Tick interval() { return _interval; } function in class:CPUProgressEvent
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| /gem5/configs/example/ |
| H A D | memtest.py | 105 help="Progress message interval "
255 # and also make the interval of packet injection longer for the
259 testers = [proto_tester(interval = 10 * (level * level + 1),
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| /gem5/src/dev/net/ |
| H A D | i8254xGBe.cc | 705 Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval();
707 "EINT: postInterrupt() curTick(): %d itr: %d interval: %d\n",
708 curTick(), regs.itr.interval(), itr_interval);
710 if (regs.itr.interval() == 0 || now ||
803 DPRINTF(Ethernet, "ITR = %#X itr.interval = %#X\n",
804 regs.itr(), regs.itr.interval());
807 if (regs.itr.interval() == 0) {
813 Tick t = curTick() + SimClock::Int::ns * 256 * regs.itr.interval();
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| H A D | i8254xGBe_defs.hh | 455 ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval
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