13116SN/A/* 23116SN/A * Copyright (c) 2006 The Regents of The University of Michigan 33116SN/A * All rights reserved. 43116SN/A * 53116SN/A * Redistribution and use in source and binary forms, with or without 63116SN/A * modification, are permitted provided that the following conditions are 73116SN/A * met: redistributions of source code must retain the above copyright 83116SN/A * notice, this list of conditions and the following disclaimer; 93116SN/A * redistributions in binary form must reproduce the above copyright 103116SN/A * notice, this list of conditions and the following disclaimer in the 113116SN/A * documentation and/or other materials provided with the distribution; 123116SN/A * neither the name of the copyright holders nor the names of its 133116SN/A * contributors may be used to endorse or promote products derived from 143116SN/A * this software without specific prior written permission. 153116SN/A * 163116SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173116SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183116SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193116SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203116SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213116SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223116SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233116SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243116SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253116SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263116SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273116SN/A * 283116SN/A * Authors: Ali Saidi 293116SN/A */ 303116SN/A 313116SN/A/* @file 323116SN/A * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers. 333116SN/A */ 344218SN/A#include "base/bitfield.hh" 353116SN/A 363116SN/Anamespace iGbReg { 373116SN/A 384263SN/A 394263SN/A// Registers used by the Intel GbE NIC 404263SN/Aconst uint32_t REG_CTRL = 0x00000; 414263SN/Aconst uint32_t REG_STATUS = 0x00008; 424263SN/Aconst uint32_t REG_EECD = 0x00010; 434263SN/Aconst uint32_t REG_EERD = 0x00014; 444263SN/Aconst uint32_t REG_CTRL_EXT = 0x00018; 454263SN/Aconst uint32_t REG_MDIC = 0x00020; 464263SN/Aconst uint32_t REG_FCAL = 0x00028; 474263SN/Aconst uint32_t REG_FCAH = 0x0002C; 484263SN/Aconst uint32_t REG_FCT = 0x00030; 494263SN/Aconst uint32_t REG_VET = 0x00038; 504263SN/Aconst uint32_t REG_PBA = 0x01000; 514263SN/Aconst uint32_t REG_ICR = 0x000C0; 524263SN/Aconst uint32_t REG_ITR = 0x000C4; 534263SN/Aconst uint32_t REG_ICS = 0x000C8; 544263SN/Aconst uint32_t REG_IMS = 0x000D0; 554263SN/Aconst uint32_t REG_IMC = 0x000D8; 564263SN/Aconst uint32_t REG_IAM = 0x000E0; 574263SN/Aconst uint32_t REG_RCTL = 0x00100; 584263SN/Aconst uint32_t REG_FCTTV = 0x00170; 594263SN/Aconst uint32_t REG_TIPG = 0x00410; 604263SN/Aconst uint32_t REG_AIFS = 0x00458; 614263SN/Aconst uint32_t REG_LEDCTL = 0x00e00; 625763SN/Aconst uint32_t REG_EICR = 0x01580; 635763SN/Aconst uint32_t REG_IVAR0 = 0x01700; 644263SN/Aconst uint32_t REG_FCRTL = 0x02160; 654263SN/Aconst uint32_t REG_FCRTH = 0x02168; 664263SN/Aconst uint32_t REG_RDBAL = 0x02800; 674263SN/Aconst uint32_t REG_RDBAH = 0x02804; 684263SN/Aconst uint32_t REG_RDLEN = 0x02808; 695763SN/Aconst uint32_t REG_SRRCTL = 0x0280C; 704263SN/Aconst uint32_t REG_RDH = 0x02810; 714263SN/Aconst uint32_t REG_RDT = 0x02818; 724263SN/Aconst uint32_t REG_RDTR = 0x02820; 734263SN/Aconst uint32_t REG_RXDCTL = 0x02828; 744263SN/Aconst uint32_t REG_RADV = 0x0282C; 754263SN/Aconst uint32_t REG_TCTL = 0x00400; 764263SN/Aconst uint32_t REG_TDBAL = 0x03800; 774263SN/Aconst uint32_t REG_TDBAH = 0x03804; 784263SN/Aconst uint32_t REG_TDLEN = 0x03808; 794263SN/Aconst uint32_t REG_TDH = 0x03810; 805763SN/Aconst uint32_t REG_TXDCA_CTL = 0x03814; 814263SN/Aconst uint32_t REG_TDT = 0x03818; 824263SN/Aconst uint32_t REG_TIDV = 0x03820; 834263SN/Aconst uint32_t REG_TXDCTL = 0x03828; 844263SN/Aconst uint32_t REG_TADV = 0x0382C; 855763SN/Aconst uint32_t REG_TDWBAL = 0x03838; 865763SN/Aconst uint32_t REG_TDWBAH = 0x0383C; 874218SN/Aconst uint32_t REG_CRCERRS = 0x04000; 884263SN/Aconst uint32_t REG_RXCSUM = 0x05000; 895763SN/Aconst uint32_t REG_RLPML = 0x05004; 905763SN/Aconst uint32_t REG_RFCTL = 0x05008; 914218SN/Aconst uint32_t REG_MTA = 0x05200; 924218SN/Aconst uint32_t REG_RAL = 0x05400; 934218SN/Aconst uint32_t REG_RAH = 0x05404; 944218SN/Aconst uint32_t REG_VFTA = 0x05600; 954218SN/A 964263SN/Aconst uint32_t REG_WUC = 0x05800; 9711810Sbaz21@cam.ac.ukconst uint32_t REG_WUFC = 0x05808; 9811810Sbaz21@cam.ac.ukconst uint32_t REG_WUS = 0x05810; 994263SN/Aconst uint32_t REG_MANC = 0x05820; 1005763SN/Aconst uint32_t REG_SWSM = 0x05B50; 1015763SN/Aconst uint32_t REG_FWSM = 0x05B54; 1025763SN/Aconst uint32_t REG_SWFWSYNC = 0x05B5C; 1033318SN/A 1043318SN/Aconst uint8_t EEPROM_READ_OPCODE_SPI = 0x03; 1053318SN/Aconst uint8_t EEPROM_RDSR_OPCODE_SPI = 0x05; 1063318SN/Aconst uint8_t EEPROM_SIZE = 64; 1074218SN/Aconst uint16_t EEPROM_CSUM = 0xBABA; 1084218SN/A 1094218SN/Aconst uint8_t VLAN_FILTER_TABLE_SIZE = 128; 1105763SN/Aconst uint8_t RCV_ADDRESS_TABLE_SIZE = 24; 1114218SN/Aconst uint8_t MULTICAST_TABLE_SIZE = 128; 1125763SN/Aconst uint32_t STATS_REGS_SIZE = 0x228; 1134218SN/A 1144263SN/A 1154263SN/A// Registers in that are accessed in the PHY 1164218SN/Aconst uint8_t PHY_PSTATUS = 0x1; 1174218SN/Aconst uint8_t PHY_PID = 0x2; 1184218SN/Aconst uint8_t PHY_EPID = 0x3; 1194218SN/Aconst uint8_t PHY_GSTATUS = 10; 1204218SN/Aconst uint8_t PHY_EPSTATUS = 15; 1214218SN/Aconst uint8_t PHY_AGC = 18; 1224218SN/A 1234263SN/A// Receive Descriptor Status Flags 1245763SN/Aconst uint16_t RXDS_DYNINT = 0x800; 1255763SN/Aconst uint16_t RXDS_UDPV = 0x400; 1265763SN/Aconst uint16_t RXDS_CRCV = 0x100; 1275763SN/Aconst uint16_t RXDS_PIF = 0x080; 1285763SN/Aconst uint16_t RXDS_IPCS = 0x040; 1295763SN/Aconst uint16_t RXDS_TCPCS = 0x020; 1305763SN/Aconst uint16_t RXDS_UDPCS = 0x010; 1315763SN/Aconst uint16_t RXDS_VP = 0x008; 1325763SN/Aconst uint16_t RXDS_IXSM = 0x004; 1335763SN/Aconst uint16_t RXDS_EOP = 0x002; 1345763SN/Aconst uint16_t RXDS_DD = 0x001; 1353116SN/A 1364263SN/A// Receive Descriptor Error Flags 1374263SN/Aconst uint8_t RXDE_RXE = 0x80; 1384263SN/Aconst uint8_t RXDE_IPE = 0x40; 1394263SN/Aconst uint8_t RXDE_TCPE = 0x20; 1404263SN/Aconst uint8_t RXDE_SEQ = 0x04; 1414263SN/Aconst uint8_t RXDE_SE = 0x02; 1424263SN/Aconst uint8_t RXDE_CE = 0x01; 1434263SN/A 1445763SN/A// Receive Descriptor Extended Error Flags 1455763SN/Aconst uint16_t RXDEE_HBO = 0x008; 1465763SN/Aconst uint16_t RXDEE_CE = 0x010; 1475763SN/Aconst uint16_t RXDEE_LE = 0x020; 1485763SN/Aconst uint16_t RXDEE_PE = 0x080; 1495763SN/Aconst uint16_t RXDEE_OSE = 0x100; 1505763SN/Aconst uint16_t RXDEE_USE = 0x200; 1515763SN/Aconst uint16_t RXDEE_TCPE = 0x400; 1525763SN/Aconst uint16_t RXDEE_IPE = 0x800; 1535763SN/A 1545763SN/A 1555763SN/A// Receive Descriptor Types 1565763SN/Aconst uint8_t RXDT_LEGACY = 0x00; 1575763SN/Aconst uint8_t RXDT_ADV_ONEBUF = 0x01; 1585763SN/Aconst uint8_t RXDT_ADV_SPLIT_A = 0x05; 1595763SN/A 1605763SN/A// Receive Descriptor Packet Types 1615763SN/Aconst uint16_t RXDP_IPV4 = 0x001; 1625763SN/Aconst uint16_t RXDP_IPV4E = 0x002; 1635763SN/Aconst uint16_t RXDP_IPV6 = 0x004; 1645763SN/Aconst uint16_t RXDP_IPV6E = 0x008; 1655763SN/Aconst uint16_t RXDP_TCP = 0x010; 1665763SN/Aconst uint16_t RXDP_UDP = 0x020; 1675763SN/Aconst uint16_t RXDP_SCTP = 0x040; 1685763SN/Aconst uint16_t RXDP_NFS = 0x080; 1695763SN/A 1704263SN/A// Interrupt types 1714263SN/Aenum IntTypes 1724263SN/A{ 1734263SN/A IT_NONE = 0x00000, //dummy value 1744263SN/A IT_TXDW = 0x00001, 1754263SN/A IT_TXQE = 0x00002, 1764263SN/A IT_LSC = 0x00004, 1774263SN/A IT_RXSEQ = 0x00008, 1784263SN/A IT_RXDMT = 0x00010, 1794263SN/A IT_RXO = 0x00040, 1804263SN/A IT_RXT = 0x00080, 1814263SN/A IT_MADC = 0x00200, 1824263SN/A IT_RXCFG = 0x00400, 1834263SN/A IT_GPI0 = 0x02000, 1844263SN/A IT_GPI1 = 0x04000, 1854263SN/A IT_TXDLOW = 0x08000, 1864263SN/A IT_SRPD = 0x10000, 1874263SN/A IT_ACK = 0x20000 1884263SN/A}; 1894263SN/A 1904263SN/A// Receive Descriptor struct 1913116SN/Astruct RxDesc { 19211320Ssteve.reinhardt@amd.com union { 1935763SN/A struct { 1945763SN/A Addr buf; 1955763SN/A uint16_t len; 1965763SN/A uint16_t csum; 1975763SN/A uint8_t status; 1985763SN/A uint8_t errors; 1995763SN/A uint16_t vlan; 2005763SN/A } legacy; 2015763SN/A struct { 2025763SN/A Addr pkt; 2035763SN/A Addr hdr; 2045763SN/A } adv_read; 2055763SN/A struct { 2065763SN/A uint16_t rss_type:4; 2075763SN/A uint16_t pkt_type:12; 2085763SN/A uint16_t __reserved1:5; 2095763SN/A uint16_t header_len:10; 2105763SN/A uint16_t sph:1; 2115763SN/A union { 2125763SN/A struct { 2135763SN/A uint16_t id; 2145763SN/A uint16_t csum; 2155763SN/A }; 2165763SN/A uint32_t rss_hash; 2175763SN/A }; 2185763SN/A uint32_t status:20; 2195763SN/A uint32_t errors:12; 2205763SN/A uint16_t pkt_len; 2215763SN/A uint16_t vlan_tag; 2225763SN/A } adv_wb ; 2235763SN/A }; 2243116SN/A}; 2253116SN/A 2264263SN/Astruct TxDesc { 2274263SN/A uint64_t d1; 2284263SN/A uint64_t d2; 2294263SN/A}; 2303116SN/A 2314263SN/Anamespace TxdOp { 2324263SN/Aconst uint8_t TXD_CNXT = 0x0; 2334291SN/Aconst uint8_t TXD_DATA = 0x1; 2345763SN/Aconst uint8_t TXD_ADVCNXT = 0x2; 2355763SN/Aconst uint8_t TXD_ADVDATA = 0x3; 2363116SN/A 2379335SN/Ainline bool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); } 2389335SN/Ainline uint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); } 2399335SN/Ainline bool isType(TxDesc *d, uint8_t type) { return getType(d) == type; } 2409335SN/Ainline bool isTypes(TxDesc *d, uint8_t t1, uint8_t t2) { return isType(d, t1) || isType(d, t2); } 2419335SN/Ainline bool isAdvDesc(TxDesc *d) { return !isLegacy(d) && isTypes(d, TXD_ADVDATA,TXD_ADVCNXT); } 2429335SN/Ainline bool isContext(TxDesc *d) { return !isLegacy(d) && isTypes(d,TXD_CNXT, TXD_ADVCNXT); } 2439335SN/Ainline bool isData(TxDesc *d) { return !isLegacy(d) && isTypes(d, TXD_DATA, TXD_ADVDATA); } 2443116SN/A 2459335SN/Ainline Addr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; } 2469335SN/Ainline Addr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); } 2479335SN/Ainline void setDd(TxDesc *d) { replaceBits(d->d2, 35, 32, ULL(1)); } 2484263SN/A 2499335SN/Ainline bool ide(TxDesc *d) { return bits(d->d2, 31,31) && (getType(d) == TXD_DATA || isLegacy(d)); } 2509335SN/Ainline bool vle(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); } 2519335SN/Ainline bool rs(TxDesc *d) { return bits(d->d2, 27,27); } 2529335SN/Ainline bool ic(TxDesc *d) { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); } 2539335SN/Ainline bool tse(TxDesc *d) { 2545763SN/A if (isTypes(d, TXD_CNXT, TXD_DATA)) 25511320Ssteve.reinhardt@amd.com return bits(d->d2, 26,26); 2565763SN/A if (isType(d, TXD_ADVDATA)) 2575763SN/A return bits(d->d2, 31, 31); 2585763SN/A return false; 2595763SN/A} 2605763SN/A 2619335SN/Ainline bool ifcs(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 25,25); } 2629335SN/Ainline bool eop(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 24,24); } 2639335SN/Ainline bool ip(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 25,25); } 2649335SN/Ainline bool tcp(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 24,24); } 2654263SN/A 2669335SN/Ainline uint8_t getCso(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 23,16); } 2679335SN/Ainline uint8_t getCss(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 47,40); } 2684263SN/A 2699335SN/Ainline bool ixsm(TxDesc *d) { return isData(d) && bits(d->d2, 40,40); } 2709335SN/Ainline bool txsm(TxDesc *d) { return isData(d) && bits(d->d2, 41,41); } 2714263SN/A 2729335SN/Ainline int tucse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,63,48); } 2739335SN/Ainline int tucso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,47,40); } 2749335SN/Ainline int tucss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,39,32); } 2759335SN/Ainline int ipcse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,31,16); } 2769335SN/Ainline int ipcso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,15,8); } 2779335SN/Ainline int ipcss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,7,0); } 2789335SN/Ainline int mss(TxDesc *d) { assert(isContext(d)); return bits(d->d2,63,48); } 2799335SN/Ainline int hdrlen(TxDesc *d) { 28011320Ssteve.reinhardt@amd.com assert(isContext(d)); 2815763SN/A if (!isAdvDesc(d)) 2825763SN/A return bits(d->d2,47,40); 28311320Ssteve.reinhardt@amd.com return bits(d->d2, 47,40) + bits(d->d1, 8,0) + bits(d->d1, 15, 9); 2845763SN/A} 2855763SN/A 2869335SN/Ainline int getTsoLen(TxDesc *d) { assert(isType(d, TXD_ADVDATA)); return bits(d->d2, 63,46); } 2879335SN/Ainline int utcmd(TxDesc *d) { assert(isContext(d)); return bits(d->d2,24,31); } 2884263SN/A} // namespace TxdOp 2894263SN/A 2903116SN/A 2914218SN/A#define ADD_FIELD32(NAME, OFFSET, BITS) \ 2924218SN/A inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 2934218SN/A inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 2944218SN/A 2954218SN/A#define ADD_FIELD64(NAME, OFFSET, BITS) \ 2964218SN/A inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 2974218SN/A inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 2984218SN/A 29910905SN/Astruct Regs : public Serializable { 3004218SN/A template<class T> 3014218SN/A struct Reg { 3024218SN/A T _data; 3034218SN/A T operator()() { return _data; } 3044218SN/A const Reg<T> &operator=(T d) { _data = d; return *this;} 3054218SN/A bool operator==(T d) { return d == _data; } 3064218SN/A void operator()(T d) { _data = d; } 3074263SN/A Reg() { _data = 0; } 30810905SN/A void serialize(CheckpointOut &cp) const 3094294SN/A { 3104294SN/A SERIALIZE_SCALAR(_data); 3114294SN/A } 31210905SN/A void unserialize(CheckpointIn &cp) 3134294SN/A { 3144294SN/A UNSERIALIZE_SCALAR(_data); 3154294SN/A } 3164218SN/A }; 3173318SN/A 3184218SN/A struct CTRL : public Reg<uint32_t> { // 0x0000 CTRL Register 3194218SN/A using Reg<uint32_t>::operator=; 3204218SN/A ADD_FIELD32(fd,0,1); // full duplex 3214218SN/A ADD_FIELD32(bem,1,1); // big endian mode 3224218SN/A ADD_FIELD32(pcipr,2,1); // PCI priority 3234218SN/A ADD_FIELD32(lrst,3,1); // link reset 3244218SN/A ADD_FIELD32(tme,4,1); // test mode enable 3254218SN/A ADD_FIELD32(asde,5,1); // Auto-speed detection 3264218SN/A ADD_FIELD32(slu,6,1); // Set link up 3274218SN/A ADD_FIELD32(ilos,7,1); // invert los-of-signal 3284218SN/A ADD_FIELD32(speed,8,2); // speed selection bits 3294218SN/A ADD_FIELD32(be32,10,1); // big endian mode 32 3304218SN/A ADD_FIELD32(frcspd,11,1); // force speed 3314218SN/A ADD_FIELD32(frcdpx,12,1); // force duplex 3324218SN/A ADD_FIELD32(duden,13,1); // dock/undock enable 3334218SN/A ADD_FIELD32(dudpol,14,1); // dock/undock polarity 3344218SN/A ADD_FIELD32(fphyrst,15,1); // force phy reset 3354218SN/A ADD_FIELD32(extlen,16,1); // external link status enable 3364218SN/A ADD_FIELD32(rsvd,17,1); // reserved 3374218SN/A ADD_FIELD32(sdp0d,18,1); // software controlled pin data 3384218SN/A ADD_FIELD32(sdp1d,19,1); // software controlled pin data 3394218SN/A ADD_FIELD32(sdp2d,20,1); // software controlled pin data 3404218SN/A ADD_FIELD32(sdp3d,21,1); // software controlled pin data 3414218SN/A ADD_FIELD32(sdp0i,22,1); // software controlled pin dir 3424218SN/A ADD_FIELD32(sdp1i,23,1); // software controlled pin dir 3434218SN/A ADD_FIELD32(sdp2i,24,1); // software controlled pin dir 3444218SN/A ADD_FIELD32(sdp3i,25,1); // software controlled pin dir 3454218SN/A ADD_FIELD32(rst,26,1); // reset 3464218SN/A ADD_FIELD32(rfce,27,1); // receive flow control enable 3474218SN/A ADD_FIELD32(tfce,28,1); // transmit flow control enable 3484218SN/A ADD_FIELD32(rte,29,1); // routing tag enable 3494218SN/A ADD_FIELD32(vme,30,1); // vlan enable 3504218SN/A ADD_FIELD32(phyrst,31,1); // phy reset 3514218SN/A }; 3524218SN/A CTRL ctrl; 3533318SN/A 3544218SN/A struct STATUS : public Reg<uint32_t> { // 0x0008 STATUS Register 3554218SN/A using Reg<uint32_t>::operator=; 3564218SN/A ADD_FIELD32(fd,0,1); // full duplex 3574218SN/A ADD_FIELD32(lu,1,1); // link up 3584218SN/A ADD_FIELD32(func,2,2); // function id 3594218SN/A ADD_FIELD32(txoff,4,1); // transmission paused 3604218SN/A ADD_FIELD32(tbimode,5,1); // tbi mode 3614218SN/A ADD_FIELD32(speed,6,2); // link speed 3624218SN/A ADD_FIELD32(asdv,8,2); // auto speed detection value 3634218SN/A ADD_FIELD32(mtxckok,10,1); // mtx clock running ok 3644218SN/A ADD_FIELD32(pci66,11,1); // In 66Mhz pci slot 3654218SN/A ADD_FIELD32(bus64,12,1); // in 64 bit slot 3664218SN/A ADD_FIELD32(pcix,13,1); // Pci mode 3674218SN/A ADD_FIELD32(pcixspd,14,2); // pci x speed 3684218SN/A }; 3694218SN/A STATUS sts; 3703318SN/A 3714218SN/A struct EECD : public Reg<uint32_t> { // 0x0010 EECD Register 3724218SN/A using Reg<uint32_t>::operator=; 3734218SN/A ADD_FIELD32(sk,0,1); // clack input to the eeprom 3744218SN/A ADD_FIELD32(cs,1,1); // chip select to eeprom 3754218SN/A ADD_FIELD32(din,2,1); // data input to eeprom 3764218SN/A ADD_FIELD32(dout,3,1); // data output bit 3774218SN/A ADD_FIELD32(fwe,4,2); // flash write enable 3784218SN/A ADD_FIELD32(ee_req,6,1); // request eeprom access 3794218SN/A ADD_FIELD32(ee_gnt,7,1); // grant eeprom access 3804218SN/A ADD_FIELD32(ee_pres,8,1); // eeprom present 3814218SN/A ADD_FIELD32(ee_size,9,1); // eeprom size 3824218SN/A ADD_FIELD32(ee_sz1,10,1); // eeprom size 3834218SN/A ADD_FIELD32(rsvd,11,2); // reserved 3844218SN/A ADD_FIELD32(ee_type,13,1); // type of eeprom 3854218SN/A } ; 3864218SN/A EECD eecd; 3873318SN/A 3884218SN/A struct EERD : public Reg<uint32_t> { // 0x0014 EERD Register 3894218SN/A using Reg<uint32_t>::operator=; 3904218SN/A ADD_FIELD32(start,0,1); // start read 3915763SN/A ADD_FIELD32(done,1,1); // done read 3925763SN/A ADD_FIELD32(addr,2,14); // address 3934218SN/A ADD_FIELD32(data,16,16); // data 3944218SN/A }; 3954218SN/A EERD eerd; 3963318SN/A 3974218SN/A struct CTRL_EXT : public Reg<uint32_t> { // 0x0018 CTRL_EXT Register 3984218SN/A using Reg<uint32_t>::operator=; 3994218SN/A ADD_FIELD32(gpi_en,0,4); // enable interrupts from gpio 4004218SN/A ADD_FIELD32(phyint,5,1); // reads the phy internal int status 4014218SN/A ADD_FIELD32(sdp2_data,6,1); // data from gpio sdp 4024218SN/A ADD_FIELD32(spd3_data,7,1); // data frmo gpio sdp 4034218SN/A ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2 4044218SN/A ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2 4054218SN/A ADD_FIELD32(asdchk,12,1); // initiate auto-speed-detection 4064218SN/A ADD_FIELD32(eerst,13,1); // reset the eeprom 4074218SN/A ADD_FIELD32(spd_byps,15,1); // bypass speed select 4084218SN/A ADD_FIELD32(ro_dis,17,1); // disable relaxed memory ordering 4094218SN/A ADD_FIELD32(vreg,21,1); // power down the voltage regulator 4104218SN/A ADD_FIELD32(link_mode,22,2); // interface to talk to the link 4114218SN/A ADD_FIELD32(iame, 27,1); // interrupt acknowledge auto-mask ?? 4124218SN/A ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device 4134218SN/A ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ?? 4144218SN/A }; 4154218SN/A CTRL_EXT ctrl_ext; 4163318SN/A 4174218SN/A struct MDIC : public Reg<uint32_t> { // 0x0020 MDIC Register 4184218SN/A using Reg<uint32_t>::operator=; 4194218SN/A ADD_FIELD32(data,0,16); // data 4204218SN/A ADD_FIELD32(regadd,16,5); // register address 4214218SN/A ADD_FIELD32(phyadd,21,5); // phy addresses 4224218SN/A ADD_FIELD32(op,26,2); // opcode 4234218SN/A ADD_FIELD32(r,28,1); // ready 4244218SN/A ADD_FIELD32(i,29,1); // interrupt 4254218SN/A ADD_FIELD32(e,30,1); // error 4264218SN/A }; 4274218SN/A MDIC mdic; 4283318SN/A 4294218SN/A struct ICR : public Reg<uint32_t> { // 0x00C0 ICR Register 4304218SN/A using Reg<uint32_t>::operator=; 4314218SN/A ADD_FIELD32(txdw,0,1) // tx descr witten back 4324218SN/A ADD_FIELD32(txqe,1,1) // tx queue empty 4334218SN/A ADD_FIELD32(lsc,2,1) // link status change 4344218SN/A ADD_FIELD32(rxseq,3,1) // rcv sequence error 4354218SN/A ADD_FIELD32(rxdmt0,4,1) // rcv descriptor min thresh 4364218SN/A ADD_FIELD32(rsvd1,5,1) // reserved 4374218SN/A ADD_FIELD32(rxo,6,1) // receive overrunn 4384218SN/A ADD_FIELD32(rxt0,7,1) // receiver timer interrupt 4394218SN/A ADD_FIELD32(mdac,9,1) // mdi/o access complete 4404218SN/A ADD_FIELD32(rxcfg,10,1) // recv /c/ ordered sets 4414218SN/A ADD_FIELD32(phyint,12,1) // phy interrupt 4424218SN/A ADD_FIELD32(gpi1,13,1) // gpi int 1 4434218SN/A ADD_FIELD32(gpi2,14,1) // gpi int 2 4444218SN/A ADD_FIELD32(txdlow,15,1) // transmit desc low thresh 4454218SN/A ADD_FIELD32(srpd,16,1) // small receive packet detected 4464218SN/A ADD_FIELD32(ack,17,1); // receive ack frame 4474283SN/A ADD_FIELD32(int_assert, 31,1); // interrupt caused a system interrupt 4484218SN/A }; 4494218SN/A ICR icr; 4503318SN/A 4514218SN/A uint32_t imr; // register that contains the current interrupt mask 4524218SN/A 4534218SN/A struct ITR : public Reg<uint32_t> { // 0x00C4 ITR Register 4544218SN/A using Reg<uint32_t>::operator=; 4554218SN/A ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval 4564218SN/A // specified in 256ns interrupts 4574218SN/A }; 4584218SN/A ITR itr; 4594218SN/A 4604218SN/A // When CTRL_EXT.IAME and the ICR.INT_ASSERT is 1 an ICR read or write 4614218SN/A // causes the IAM register contents to be written into the IMC 4624218SN/A // automatically clearing all interrupts that have a bit in the IAM set 4634218SN/A uint32_t iam; 4644218SN/A 4654218SN/A struct RCTL : public Reg<uint32_t> { // 0x0100 RCTL Register 4664218SN/A using Reg<uint32_t>::operator=; 4674218SN/A ADD_FIELD32(rst,0,1); // Reset 4684218SN/A ADD_FIELD32(en,1,1); // Enable 4694218SN/A ADD_FIELD32(sbp,2,1); // Store bad packets 4704218SN/A ADD_FIELD32(upe,3,1); // Unicast Promiscuous enabled 4714218SN/A ADD_FIELD32(mpe,4,1); // Multicast promiscuous enabled 4724218SN/A ADD_FIELD32(lpe,5,1); // long packet reception enabled 4734218SN/A ADD_FIELD32(lbm,6,2); // 4744218SN/A ADD_FIELD32(rdmts,8,2); // 4754218SN/A ADD_FIELD32(mo,12,2); // 4764218SN/A ADD_FIELD32(mdr,14,1); // 4774218SN/A ADD_FIELD32(bam,15,1); // 4784218SN/A ADD_FIELD32(bsize,16,2); // 4794218SN/A ADD_FIELD32(vfe,18,1); // 4804218SN/A ADD_FIELD32(cfien,19,1); // 4814218SN/A ADD_FIELD32(cfi,20,1); // 4824218SN/A ADD_FIELD32(dpf,22,1); // discard pause frames 4834218SN/A ADD_FIELD32(pmcf,23,1); // pass mac control frames 4844218SN/A ADD_FIELD32(bsex,25,1); // buffer size extension 4854218SN/A ADD_FIELD32(secrc,26,1); // strip ethernet crc from incoming packet 4866227SN/A unsigned descSize() 4874263SN/A { 4884263SN/A switch(bsize()) { 4897779SN/A case 0: return bsex() == 0 ? 2048 : 0; 4904283SN/A case 1: return bsex() == 0 ? 1024 : 16384; 4914283SN/A case 2: return bsex() == 0 ? 512 : 8192; 4924283SN/A case 3: return bsex() == 0 ? 256 : 4096; 4934263SN/A default: 4947779SN/A return 0; 4954263SN/A } 4964263SN/A } 4974218SN/A }; 4984218SN/A RCTL rctl; 4994218SN/A 5004218SN/A struct FCTTV : public Reg<uint32_t> { // 0x0170 FCTTV 5014218SN/A using Reg<uint32_t>::operator=; 5024218SN/A ADD_FIELD32(ttv,0,16); // Transmit Timer Value 5034218SN/A }; 5044218SN/A FCTTV fcttv; 5054218SN/A 5064218SN/A struct TCTL : public Reg<uint32_t> { // 0x0400 TCTL Register 5074218SN/A using Reg<uint32_t>::operator=; 5084218SN/A ADD_FIELD32(rst,0,1); // Reset 5094218SN/A ADD_FIELD32(en,1,1); // Enable 5104218SN/A ADD_FIELD32(bce,2,1); // busy check enable 5114218SN/A ADD_FIELD32(psp,3,1); // pad short packets 5124218SN/A ADD_FIELD32(ct,4,8); // collision threshold 5134218SN/A ADD_FIELD32(cold,12,10); // collision distance 5144218SN/A ADD_FIELD32(swxoff,22,1); // software xoff transmission 5154218SN/A ADD_FIELD32(pbe,23,1); // packet burst enable 5164218SN/A ADD_FIELD32(rtlc,24,1); // retransmit late collisions 5174218SN/A ADD_FIELD32(nrtu,25,1); // on underrun no TX 5184218SN/A ADD_FIELD32(mulr,26,1); // multiple request 5194218SN/A }; 5204218SN/A TCTL tctl; 5214218SN/A 5224218SN/A struct PBA : public Reg<uint32_t> { // 0x1000 PBA Register 5234218SN/A using Reg<uint32_t>::operator=; 5244218SN/A ADD_FIELD32(rxa,0,16); 5254218SN/A ADD_FIELD32(txa,16,16); 5264218SN/A }; 5274218SN/A PBA pba; 5284218SN/A 5294218SN/A struct FCRTL : public Reg<uint32_t> { // 0x2160 FCRTL Register 5304218SN/A using Reg<uint32_t>::operator=; 5314218SN/A ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have 5324218SN/A // a larger buffer 5334218SN/A ADD_FIELD32(xone, 31,1); 5344218SN/A }; 5354218SN/A FCRTL fcrtl; 5364218SN/A 5374218SN/A struct FCRTH : public Reg<uint32_t> { // 0x2168 FCRTL Register 5384218SN/A using Reg<uint32_t>::operator=; 5394218SN/A ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have 5404218SN/A //a larger buffer 5414218SN/A ADD_FIELD32(xfce, 31,1); 5424218SN/A }; 5434218SN/A FCRTH fcrth; 5444218SN/A 5454218SN/A struct RDBA : public Reg<uint64_t> { // 0x2800 RDBA Register 5464218SN/A using Reg<uint64_t>::operator=; 5474283SN/A ADD_FIELD64(rdbal,0,32); // base address of rx descriptor ring 5484218SN/A ADD_FIELD64(rdbah,32,32); // base address of rx descriptor ring 5494218SN/A }; 5504218SN/A RDBA rdba; 5514218SN/A 5524218SN/A struct RDLEN : public Reg<uint32_t> { // 0x2808 RDLEN Register 5534218SN/A using Reg<uint32_t>::operator=; 5544218SN/A ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer 5554218SN/A }; 5564218SN/A RDLEN rdlen; 5574218SN/A 5585763SN/A struct SRRCTL : public Reg<uint32_t> { // 0x280C SRRCTL Register 5595763SN/A using Reg<uint32_t>::operator=; 5605783SN/A ADD_FIELD32(pktlen, 0, 8); 5615783SN/A ADD_FIELD32(hdrlen, 8, 8); // guess based on header, not documented 5625763SN/A ADD_FIELD32(desctype, 25,3); // type of descriptor 000 legacy, 001 adv, 5635763SN/A //101 hdr split 5646227SN/A unsigned bufLen() { return pktlen() << 10; } 5656227SN/A unsigned hdrLen() { return hdrlen() << 6; } 5665763SN/A }; 5675763SN/A SRRCTL srrctl; 5685763SN/A 5694218SN/A struct RDH : public Reg<uint32_t> { // 0x2810 RDH Register 5704218SN/A using Reg<uint32_t>::operator=; 5714218SN/A ADD_FIELD32(rdh,0,16); // head of the descriptor ring 5724218SN/A }; 5734218SN/A RDH rdh; 5744218SN/A 5754218SN/A struct RDT : public Reg<uint32_t> { // 0x2818 RDT Register 5764218SN/A using Reg<uint32_t>::operator=; 5774218SN/A ADD_FIELD32(rdt,0,16); // tail of the descriptor ring 5784218SN/A }; 5794218SN/A RDT rdt; 5804218SN/A 5814218SN/A struct RDTR : public Reg<uint32_t> { // 0x2820 RDTR Register 5824218SN/A using Reg<uint32_t>::operator=; 5834218SN/A ADD_FIELD32(delay,0,16); // receive delay timer 5844263SN/A ADD_FIELD32(fpd, 31,1); // flush partial descriptor block ?? 5854218SN/A }; 5864218SN/A RDTR rdtr; 5874218SN/A 5884263SN/A struct RXDCTL : public Reg<uint32_t> { // 0x2828 RXDCTL Register 5894263SN/A using Reg<uint32_t>::operator=; 5904263SN/A ADD_FIELD32(pthresh,0,6); // prefetch threshold, less that this 5914263SN/A // consider prefetch 5924263SN/A ADD_FIELD32(hthresh,8,6); // number of descriptors in host mem to 5934263SN/A // consider prefetch 5944263SN/A ADD_FIELD32(wthresh,16,6); // writeback threshold 5954263SN/A ADD_FIELD32(gran,24,1); // granularity 0 = desc, 1 = cacheline 5964263SN/A }; 5974263SN/A RXDCTL rxdctl; 5984263SN/A 5994218SN/A struct RADV : public Reg<uint32_t> { // 0x282C RADV Register 6004218SN/A using Reg<uint32_t>::operator=; 6014218SN/A ADD_FIELD32(idv,0,16); // absolute interrupt delay 6024218SN/A }; 6034218SN/A RADV radv; 6044218SN/A 6054218SN/A struct RSRPD : public Reg<uint32_t> { // 0x2C00 RSRPD Register 6064218SN/A using Reg<uint32_t>::operator=; 6074218SN/A ADD_FIELD32(idv,0,12); // size to interrutp on small packets 6084218SN/A }; 6094218SN/A RSRPD rsrpd; 6104218SN/A 6114218SN/A struct TDBA : public Reg<uint64_t> { // 0x3800 TDBAL Register 6124218SN/A using Reg<uint64_t>::operator=; 6134283SN/A ADD_FIELD64(tdbal,0,32); // base address of transmit descriptor ring 6144218SN/A ADD_FIELD64(tdbah,32,32); // base address of transmit descriptor ring 6154218SN/A }; 6164218SN/A TDBA tdba; 6174218SN/A 6184218SN/A struct TDLEN : public Reg<uint32_t> { // 0x3808 TDLEN Register 6194218SN/A using Reg<uint32_t>::operator=; 6204218SN/A ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer 6214218SN/A }; 6224218SN/A TDLEN tdlen; 6234218SN/A 6244218SN/A struct TDH : public Reg<uint32_t> { // 0x3810 TDH Register 6254218SN/A using Reg<uint32_t>::operator=; 6264218SN/A ADD_FIELD32(tdh,0,16); // head of the descriptor ring 6274218SN/A }; 6284218SN/A TDH tdh; 6294218SN/A 6305763SN/A struct TXDCA_CTL : public Reg<uint32_t> { // 0x3814 TXDCA_CTL Register 6315763SN/A using Reg<uint32_t>::operator=; 6325763SN/A ADD_FIELD32(cpu_mask, 0, 5); 6335763SN/A ADD_FIELD32(enabled, 5,1); 6345763SN/A ADD_FIELD32(relax_ordering, 6, 1); 6355763SN/A }; 6365763SN/A TXDCA_CTL txdca_ctl; 6375763SN/A 6384218SN/A struct TDT : public Reg<uint32_t> { // 0x3818 TDT Register 6394218SN/A using Reg<uint32_t>::operator=; 6404218SN/A ADD_FIELD32(tdt,0,16); // tail of the descriptor ring 6414218SN/A }; 6424218SN/A TDT tdt; 6434218SN/A 6444218SN/A struct TIDV : public Reg<uint32_t> { // 0x3820 TIDV Register 6454218SN/A using Reg<uint32_t>::operator=; 6464218SN/A ADD_FIELD32(idv,0,16); // interrupt delay 6474218SN/A }; 6484218SN/A TIDV tidv; 6494218SN/A 6504218SN/A struct TXDCTL : public Reg<uint32_t> { // 0x3828 TXDCTL Register 6514218SN/A using Reg<uint32_t>::operator=; 6524218SN/A ADD_FIELD32(pthresh, 0,6); // if number of descriptors control has is 6534218SN/A // below this number, a prefetch is considered 6544218SN/A ADD_FIELD32(hthresh,8,8); // number of valid descriptors is host memory 6554218SN/A // before a prefetch is considered 6564218SN/A ADD_FIELD32(wthresh,16,6); // number of descriptors to keep until 6574218SN/A // writeback is considered 6584218SN/A ADD_FIELD32(gran, 24,1); // granulatiry of above values (0 = cacheline, 6594218SN/A // 1 == desscriptor) 6604218SN/A ADD_FIELD32(lwthresh,25,7); // xmit descriptor low thresh, interrupt 6614218SN/A // below this level 6624218SN/A }; 6634218SN/A TXDCTL txdctl; 6644218SN/A 6654218SN/A struct TADV : public Reg<uint32_t> { // 0x382C TADV Register 6664218SN/A using Reg<uint32_t>::operator=; 6674218SN/A ADD_FIELD32(idv,0,16); // absolute interrupt delay 6684218SN/A }; 6694218SN/A TADV tadv; 6705763SN/A/* 6715763SN/A struct TDWBA : public Reg<uint64_t> { // 0x3838 TDWBA Register 6725763SN/A using Reg<uint64_t>::operator=; 6735763SN/A ADD_FIELD64(en,0,1); // enable transmit description ring address writeback 6745763SN/A ADD_FIELD64(tdwbal,2,32); // base address of transmit descriptor ring address writeback 6755763SN/A ADD_FIELD64(tdwbah,32,32); // base address of transmit descriptor ring 6765763SN/A }; 6775763SN/A TDWBA tdwba;*/ 6785763SN/A uint64_t tdwba; 6794218SN/A 6804218SN/A struct RXCSUM : public Reg<uint32_t> { // 0x5000 RXCSUM Register 6814218SN/A using Reg<uint32_t>::operator=; 6824218SN/A ADD_FIELD32(pcss,0,8); 6834218SN/A ADD_FIELD32(ipofld,8,1); 6844218SN/A ADD_FIELD32(tuofld,9,1); 6855763SN/A ADD_FIELD32(pcsd, 13,1); 6864218SN/A }; 6874218SN/A RXCSUM rxcsum; 6884218SN/A 6895763SN/A uint32_t rlpml; // 0x5004 RLPML probably maximum accepted packet size 6905763SN/A 6915763SN/A struct RFCTL : public Reg<uint32_t> { // 0x5008 RFCTL Register 6925763SN/A using Reg<uint32_t>::operator=; 6935763SN/A ADD_FIELD32(iscsi_dis,0,1); 6945763SN/A ADD_FIELD32(iscsi_dwc,1,5); 6955763SN/A ADD_FIELD32(nfsw_dis,6,1); 6965763SN/A ADD_FIELD32(nfsr_dis,7,1); 6975763SN/A ADD_FIELD32(nfs_ver,8,2); 6985763SN/A ADD_FIELD32(ipv6_dis,10,1); 6995763SN/A ADD_FIELD32(ipv6xsum_dis,11,1); 7005763SN/A ADD_FIELD32(ackdis,13,1); 7015763SN/A ADD_FIELD32(ipfrsp_dis,14,1); 7025763SN/A ADD_FIELD32(exsten,15,1); 7035763SN/A }; 7045763SN/A RFCTL rfctl; 7055763SN/A 7064218SN/A struct MANC : public Reg<uint32_t> { // 0x5820 MANC Register 7074218SN/A using Reg<uint32_t>::operator=; 7084218SN/A ADD_FIELD32(smbus,0,1); // SMBus enabled ##### 7094218SN/A ADD_FIELD32(asf,1,1); // ASF enabled ##### 7104218SN/A ADD_FIELD32(ronforce,2,1); // reset of force 7114218SN/A ADD_FIELD32(rsvd,3,5); // reserved 7124218SN/A ADD_FIELD32(rmcp1,8,1); // rcmp1 filtering 7134218SN/A ADD_FIELD32(rmcp2,9,1); // rcmp2 filtering 7144218SN/A ADD_FIELD32(ipv4,10,1); // enable ipv4 7154218SN/A ADD_FIELD32(ipv6,11,1); // enable ipv6 7164218SN/A ADD_FIELD32(snap,12,1); // accept snap 7174218SN/A ADD_FIELD32(arp,13,1); // filter arp ##### 7184218SN/A ADD_FIELD32(neighbor,14,1); // neighbor discovery 7194218SN/A ADD_FIELD32(arp_resp,15,1); // arp response 7204218SN/A ADD_FIELD32(tcorst,16,1); // tco reset happened 7214218SN/A ADD_FIELD32(rcvtco,17,1); // receive tco enabled ###### 7224218SN/A ADD_FIELD32(blkphyrst,18,1);// block phy resets ######## 7234218SN/A ADD_FIELD32(rcvall,19,1); // receive all 7244218SN/A ADD_FIELD32(macaddrfltr,20,1); // mac address filtering ###### 7254218SN/A ADD_FIELD32(mng2host,21,1); // mng2 host packets ####### 7264218SN/A ADD_FIELD32(ipaddrfltr,22,1); // ip address filtering 7274218SN/A ADD_FIELD32(xsumfilter,23,1); // checksum filtering 7284218SN/A ADD_FIELD32(brfilter,24,1); // broadcast filtering 7294218SN/A ADD_FIELD32(smbreq,25,1); // smb request 7304218SN/A ADD_FIELD32(smbgnt,26,1); // smb grant 7314218SN/A ADD_FIELD32(smbclkin,27,1); // smbclkin 7324218SN/A ADD_FIELD32(smbdatain,28,1); // smbdatain 7334218SN/A ADD_FIELD32(smbdataout,29,1); // smb data out 7344218SN/A ADD_FIELD32(smbclkout,30,1); // smb clock out 7354218SN/A }; 7364218SN/A MANC manc; 7374294SN/A 7385763SN/A struct SWSM : public Reg<uint32_t> { // 0x5B50 SWSM register 7395763SN/A using Reg<uint32_t>::operator=; 7405763SN/A ADD_FIELD32(smbi,0,1); // Semaphone bit 7415763SN/A ADD_FIELD32(swesmbi, 1,1); // Software eeporm semaphore 7425763SN/A ADD_FIELD32(wmng, 2,1); // Wake MNG clock 7435763SN/A ADD_FIELD32(reserved, 3, 29); 7445763SN/A }; 7455763SN/A SWSM swsm; 7465763SN/A 7475763SN/A struct FWSM : public Reg<uint32_t> { // 0x5B54 FWSM register 7485763SN/A using Reg<uint32_t>::operator=; 74911320Ssteve.reinhardt@amd.com ADD_FIELD32(eep_fw_semaphore,0,1); 75011320Ssteve.reinhardt@amd.com ADD_FIELD32(fw_mode, 1,3); 75111320Ssteve.reinhardt@amd.com ADD_FIELD32(ide, 4,1); 7525763SN/A ADD_FIELD32(sol, 5,1); 7535763SN/A ADD_FIELD32(eep_roload, 6,1); 7545763SN/A ADD_FIELD32(reserved, 7,8); 7555763SN/A ADD_FIELD32(fw_val_bit, 15, 1); 7565763SN/A ADD_FIELD32(reset_cnt, 16, 3); 7575763SN/A ADD_FIELD32(ext_err_ind, 19, 6); 7585763SN/A ADD_FIELD32(reserved2, 25, 7); 7595763SN/A }; 7605763SN/A FWSM fwsm; 7615763SN/A 7625763SN/A uint32_t sw_fw_sync; 7635763SN/A 76411168SN/A void serialize(CheckpointOut &cp) const override 7654294SN/A { 76610905SN/A paramOut(cp, "ctrl", ctrl._data); 76710905SN/A paramOut(cp, "sts", sts._data); 76810905SN/A paramOut(cp, "eecd", eecd._data); 76910905SN/A paramOut(cp, "eerd", eerd._data); 77010905SN/A paramOut(cp, "ctrl_ext", ctrl_ext._data); 77110905SN/A paramOut(cp, "mdic", mdic._data); 77210905SN/A paramOut(cp, "icr", icr._data); 7734294SN/A SERIALIZE_SCALAR(imr); 77410905SN/A paramOut(cp, "itr", itr._data); 7754294SN/A SERIALIZE_SCALAR(iam); 77610905SN/A paramOut(cp, "rctl", rctl._data); 77710905SN/A paramOut(cp, "fcttv", fcttv._data); 77810905SN/A paramOut(cp, "tctl", tctl._data); 77910905SN/A paramOut(cp, "pba", pba._data); 78010905SN/A paramOut(cp, "fcrtl", fcrtl._data); 78110905SN/A paramOut(cp, "fcrth", fcrth._data); 78210905SN/A paramOut(cp, "rdba", rdba._data); 78310905SN/A paramOut(cp, "rdlen", rdlen._data); 78410905SN/A paramOut(cp, "srrctl", srrctl._data); 78510905SN/A paramOut(cp, "rdh", rdh._data); 78610905SN/A paramOut(cp, "rdt", rdt._data); 78710905SN/A paramOut(cp, "rdtr", rdtr._data); 78810905SN/A paramOut(cp, "rxdctl", rxdctl._data); 78910905SN/A paramOut(cp, "radv", radv._data); 79010905SN/A paramOut(cp, "rsrpd", rsrpd._data); 79110905SN/A paramOut(cp, "tdba", tdba._data); 79210905SN/A paramOut(cp, "tdlen", tdlen._data); 79310905SN/A paramOut(cp, "tdh", tdh._data); 79410905SN/A paramOut(cp, "txdca_ctl", txdca_ctl._data); 79510905SN/A paramOut(cp, "tdt", tdt._data); 79610905SN/A paramOut(cp, "tidv", tidv._data); 79710905SN/A paramOut(cp, "txdctl", txdctl._data); 79810905SN/A paramOut(cp, "tadv", tadv._data); 79910905SN/A //paramOut(cp, "tdwba", tdwba._data); 8005763SN/A SERIALIZE_SCALAR(tdwba); 80110905SN/A paramOut(cp, "rxcsum", rxcsum._data); 8025763SN/A SERIALIZE_SCALAR(rlpml); 80310905SN/A paramOut(cp, "rfctl", rfctl._data); 80410905SN/A paramOut(cp, "manc", manc._data); 80510905SN/A paramOut(cp, "swsm", swsm._data); 80610905SN/A paramOut(cp, "fwsm", fwsm._data); 8075763SN/A SERIALIZE_SCALAR(sw_fw_sync); 8084294SN/A } 8094294SN/A 81011168SN/A void unserialize(CheckpointIn &cp) override 8114294SN/A { 81210905SN/A paramIn(cp, "ctrl", ctrl._data); 81310905SN/A paramIn(cp, "sts", sts._data); 81410905SN/A paramIn(cp, "eecd", eecd._data); 81510905SN/A paramIn(cp, "eerd", eerd._data); 81610905SN/A paramIn(cp, "ctrl_ext", ctrl_ext._data); 81710905SN/A paramIn(cp, "mdic", mdic._data); 81810905SN/A paramIn(cp, "icr", icr._data); 8194294SN/A UNSERIALIZE_SCALAR(imr); 82010905SN/A paramIn(cp, "itr", itr._data); 8214294SN/A UNSERIALIZE_SCALAR(iam); 82210905SN/A paramIn(cp, "rctl", rctl._data); 82310905SN/A paramIn(cp, "fcttv", fcttv._data); 82410905SN/A paramIn(cp, "tctl", tctl._data); 82510905SN/A paramIn(cp, "pba", pba._data); 82610905SN/A paramIn(cp, "fcrtl", fcrtl._data); 82710905SN/A paramIn(cp, "fcrth", fcrth._data); 82810905SN/A paramIn(cp, "rdba", rdba._data); 82910905SN/A paramIn(cp, "rdlen", rdlen._data); 83010905SN/A paramIn(cp, "srrctl", srrctl._data); 83110905SN/A paramIn(cp, "rdh", rdh._data); 83210905SN/A paramIn(cp, "rdt", rdt._data); 83310905SN/A paramIn(cp, "rdtr", rdtr._data); 83410905SN/A paramIn(cp, "rxdctl", rxdctl._data); 83510905SN/A paramIn(cp, "radv", radv._data); 83610905SN/A paramIn(cp, "rsrpd", rsrpd._data); 83710905SN/A paramIn(cp, "tdba", tdba._data); 83810905SN/A paramIn(cp, "tdlen", tdlen._data); 83910905SN/A paramIn(cp, "tdh", tdh._data); 84010905SN/A paramIn(cp, "txdca_ctl", txdca_ctl._data); 84110905SN/A paramIn(cp, "tdt", tdt._data); 84210905SN/A paramIn(cp, "tidv", tidv._data); 84310905SN/A paramIn(cp, "txdctl", txdctl._data); 84410905SN/A paramIn(cp, "tadv", tadv._data); 8455763SN/A UNSERIALIZE_SCALAR(tdwba); 84610905SN/A //paramIn(cp, "tdwba", tdwba._data); 84710905SN/A paramIn(cp, "rxcsum", rxcsum._data); 8485763SN/A UNSERIALIZE_SCALAR(rlpml); 84910905SN/A paramIn(cp, "rfctl", rfctl._data); 85010905SN/A paramIn(cp, "manc", manc._data); 85110905SN/A paramIn(cp, "swsm", swsm._data); 85210905SN/A paramIn(cp, "fwsm", fwsm._data); 8535763SN/A UNSERIALIZE_SCALAR(sw_fw_sync); 8544294SN/A } 8553318SN/A}; 8567811SN/A} // namespace iGbReg 857