1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40#          Andreas Hansson
41from m5.params import *
42from m5.proxy import *
43
44from m5.objects.ClockedObject import ClockedObject
45
46class MemTest(ClockedObject):
47    type = 'MemTest'
48    cxx_header = "cpu/testers/memtest/memtest.hh"
49
50    # Interval of packet injection, the size of the memory range
51    # touched, and an optional stop condition
52    interval = Param.Cycles(1, "Interval between request packets")
53    size = Param.Unsigned(65536, "Size of memory region to use (bytes)")
54    max_loads = Param.Counter(0, "Number of loads to execute before exiting")
55
56    # Control the mix of packets and if functional accesses are part of
57    # the mix or not
58    percent_reads = Param.Percent(65, "Percentage reads")
59    percent_functional = Param.Percent(50, "Percentage functional accesses")
60    percent_uncacheable = Param.Percent(10, "Percentage uncacheable")
61
62    # Determine how often to print progress messages and what timeout
63    # to use for checking progress of both requests and responses
64    progress_interval = Param.Counter(1000000,
65        "Progress report interval (in accesses)")
66    progress_check = Param.Cycles(5000000, "Cycles before exiting " \
67                                      "due to lack of progress")
68
69    port = MasterPort("Port to the memory system")
70    system = Param.System(Parent.any, "System this tester is part of")
71
72    # Add the ability to supress error responses on functional
73    # accesses as Ruby needs this
74    suppress_func_warnings = Param.Bool(False, "Suppress warnings when "\
75                                            "functional accesses fail.")
76