12SN/A/* 210688Sandreas.hansson@arm.com * Copyright (c) 2015 ARM Limited 310688Sandreas.hansson@arm.com * All rights reserved 410688Sandreas.hansson@arm.com * 510688Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 610688Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 710688Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 810688Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 910688Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1010688Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1110688Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1210688Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1310688Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Erik Hallnor 412665SN/A * Steve Reinhardt 4210688Sandreas.hansson@arm.com * Andreas Hansson 432SN/A */ 442SN/A 451400SN/A#ifndef __CPU_MEMTEST_MEMTEST_HH__ 461400SN/A#define __CPU_MEMTEST_MEMTEST_HH__ 472SN/A 481298SN/A#include <set> 4910688Sandreas.hansson@arm.com#include <unordered_map> 501298SN/A 511298SN/A#include "base/statistics.hh" 5213892Sgabeblack@google.com#include "mem/port.hh" 535034SN/A#include "params/MemTest.hh" 5413892Sgabeblack@google.com#include "sim/clocked_object.hh" 551400SN/A#include "sim/eventq.hh" 56695SN/A#include "sim/stats.hh" 572SN/A 5810688Sandreas.hansson@arm.com/** 5910688Sandreas.hansson@arm.com * The MemTest class tests a cache coherent memory system by 6010688Sandreas.hansson@arm.com * generating false sharing and verifying the read data against a 6110688Sandreas.hansson@arm.com * reference updated on the completion of writes. Each tester reads 6210688Sandreas.hansson@arm.com * and writes a specific byte in a cache line, as determined by its 6310688Sandreas.hansson@arm.com * unique id. Thus, all requests issued by the MemTest instance are a 6410688Sandreas.hansson@arm.com * single byte and a specific address is only ever touched by a single 6510688Sandreas.hansson@arm.com * tester. 6610688Sandreas.hansson@arm.com * 6710688Sandreas.hansson@arm.com * In addition to verifying the data, the tester also has timeouts for 6810688Sandreas.hansson@arm.com * both requests and responses, thus checking that the memory-system 6910688Sandreas.hansson@arm.com * is making progress. 7010688Sandreas.hansson@arm.com */ 7113892Sgabeblack@google.comclass MemTest : public ClockedObject 722SN/A{ 7310688Sandreas.hansson@arm.com 742SN/A public: 7510688Sandreas.hansson@arm.com 765034SN/A typedef MemTestParams Params; 775034SN/A MemTest(const Params *p); 782SN/A 7913799SAndrea.Mondelli@ucf.edu void regStats() override; 801634SN/A 8113784Sgabeblack@google.com Port &getPort(const std::string &if_name, 8213784Sgabeblack@google.com PortID idx=InvalidPortID) override; 833187SN/A 8410688Sandreas.hansson@arm.com protected: 855314SN/A 8610688Sandreas.hansson@arm.com void tick(); 875606SN/A 8812085Sspwilson2@wisc.edu EventFunctionWrapper tickEvent; 892SN/A 9010688Sandreas.hansson@arm.com void noRequest(); 9110688Sandreas.hansson@arm.com 9212085Sspwilson2@wisc.edu EventFunctionWrapper noRequestEvent; 9310688Sandreas.hansson@arm.com 9410688Sandreas.hansson@arm.com void noResponse(); 9510688Sandreas.hansson@arm.com 9612085Sspwilson2@wisc.edu EventFunctionWrapper noResponseEvent; 974474SN/A 988922Swilliam.wang@arm.com class CpuPort : public MasterPort 993187SN/A { 10010688Sandreas.hansson@arm.com MemTest &memtest; 1013187SN/A 1023187SN/A public: 1033187SN/A 10410688Sandreas.hansson@arm.com CpuPort(const std::string &_name, MemTest &_memtest) 10510688Sandreas.hansson@arm.com : MasterPort(_name, &_memtest), memtest(_memtest) 1063187SN/A { } 1073187SN/A 1083187SN/A protected: 1093187SN/A 11010688Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt); 1113187SN/A 11210688Sandreas.hansson@arm.com void recvTimingSnoopReq(PacketPtr pkt) { } 1133187SN/A 11410688Sandreas.hansson@arm.com void recvFunctionalSnoop(PacketPtr pkt) { } 1158948Sandreas.hansson@arm.com 11610688Sandreas.hansson@arm.com Tick recvAtomicSnoop(PacketPtr pkt) { return 0; } 1173187SN/A 11810713Sandreas.hansson@arm.com void recvReqRetry(); 1193187SN/A }; 1203187SN/A 12110688Sandreas.hansson@arm.com CpuPort port; 1223187SN/A 1233349SN/A PacketPtr retryPkt; 1243187SN/A 12510688Sandreas.hansson@arm.com const unsigned size; 1262SN/A 12710688Sandreas.hansson@arm.com const Cycles interval; 1282SN/A 12910688Sandreas.hansson@arm.com const unsigned percentReads; 13010688Sandreas.hansson@arm.com const unsigned percentFunctional; 13110688Sandreas.hansson@arm.com const unsigned percentUncacheable; 1327544SN/A 1338832SAli.Saidi@ARM.com /** Request id for all generated traffic */ 1348832SAli.Saidi@ARM.com MasterID masterId; 1358832SAli.Saidi@ARM.com 13610688Sandreas.hansson@arm.com unsigned int id; 1371298SN/A 13810688Sandreas.hansson@arm.com std::set<Addr> outstandingAddrs; 1391298SN/A 14010688Sandreas.hansson@arm.com // store the expected value for the addresses we have touched 14110688Sandreas.hansson@arm.com std::unordered_map<Addr, uint8_t> referenceData; 1422SN/A 14310688Sandreas.hansson@arm.com const unsigned blockSize; 1442SN/A 14510688Sandreas.hansson@arm.com const Addr blockAddrMask; 14610688Sandreas.hansson@arm.com 14710688Sandreas.hansson@arm.com /** 14810688Sandreas.hansson@arm.com * Get the block aligned address. 14910688Sandreas.hansson@arm.com * 15010688Sandreas.hansson@arm.com * @param addr Address to align 15110688Sandreas.hansson@arm.com * @return The block aligned address 15210688Sandreas.hansson@arm.com */ 15310688Sandreas.hansson@arm.com Addr blockAlign(Addr addr) const 1542SN/A { 1552SN/A return (addr & ~blockAddrMask); 1562SN/A } 1572SN/A 15810688Sandreas.hansson@arm.com Addr baseAddr1; 15910688Sandreas.hansson@arm.com Addr baseAddr2; 1602SN/A Addr uncacheAddr; 1612SN/A 16210688Sandreas.hansson@arm.com const unsigned progressInterval; // frequency of progress reports 16310688Sandreas.hansson@arm.com const Cycles progressCheck; 1645543SN/A Tick nextProgressMessage; // access # for next progress report 1652SN/A 166695SN/A uint64_t numReads; 1678436SBrad.Beckmann@amd.com uint64_t numWrites; 16810688Sandreas.hansson@arm.com const uint64_t maxLoads; 1693262SN/A 17010688Sandreas.hansson@arm.com const bool atomic; 17110688Sandreas.hansson@arm.com 17210688Sandreas.hansson@arm.com const bool suppressFuncWarnings; 1733262SN/A 1745999SN/A Stats::Scalar numReadsStat; 1755999SN/A Stats::Scalar numWritesStat; 1762SN/A 17710688Sandreas.hansson@arm.com /** 17810688Sandreas.hansson@arm.com * Complete a request by checking the response. 17910688Sandreas.hansson@arm.com * 18010688Sandreas.hansson@arm.com * @param pkt Response packet 18110688Sandreas.hansson@arm.com * @param functional Whether the access was functional or not 18210688Sandreas.hansson@arm.com */ 18310688Sandreas.hansson@arm.com void completeRequest(PacketPtr pkt, bool functional = false); 1843187SN/A 18510688Sandreas.hansson@arm.com bool sendPkt(PacketPtr pkt); 1863262SN/A 18710688Sandreas.hansson@arm.com void recvRetry(); 1882SN/A 1892SN/A}; 1902SN/A 1911400SN/A#endif // __CPU_MEMTEST_MEMTEST_HH__ 192