xref: /gem5/src/cpu/simple/AtomicSimpleCPU.py

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# Authors: Nathan Binkert

from m5.params import *
from m5.objects.BaseSimpleCPU import BaseSimpleCPU
from m5.objects.SimPoint import SimPoint

class AtomicSimpleCPU(BaseSimpleCPU):
    """Simple CPU model executing a configurable number of
    instructions per cycle. This model uses the simplified 'atomic'
    memory mode."""

    type = 'AtomicSimpleCPU'
    cxx_header = "cpu/simple/atomic.hh"

    @classmethod
    def memory_mode(cls):
        return 'atomic'

    @classmethod
    def support_take_over(cls):
        return True

    width = Param.Int(1, "CPU width")
    simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
    simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")

    def addSimPointProbe(self, interval):
        simpoint = SimPoint()
        simpoint.interval = interval
        self.probeListener = simpoint