Searched refs:VecRegContainer (Results 1 - 25 of 29) sorted by relevance

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/gem5/src/arch/generic/
H A Dvec_reg.hh50 * bytes, unaware of anything else. This is implemented by VecRegContainer.
56 * A VecRegT is a view of a VecRegContainer (by reference). The VecRegT has
68 * the corresponding bytes of the underlying VecRegContainer through a
71 * The intended usage is requesting views to the VecRegContainer via the
77 * using Vec512 = VecRegContainer<64>;
160 class VecRegContainer;
164 * registers. There is a VecRegContainer that implements the model, and
181 const VecRegContainer<SIZE>,
182 VecRegContainer<SIZE>>::type;
253 * Cast to VecRegContainer
272 class VecRegContainer class
286 VecRegContainer() {} function in class:VecRegContainer
288 VecRegContainer(const std::vector<uint8_t>& that) function in class:VecRegContainer
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/gem5/src/arch/null/
H A Dregisters.hh56 using VecRegContainer = ::DummyVecRegContainer;
/gem5/src/cpu/
H A Dinst_res.hh49 using VecRegContainer = TheISA::VecRegContainer;
56 VecRegContainer vector;
91 explicit InstResult(const VecRegContainer& v, const ResultType& t)
182 const VecRegContainer&
H A Dthread_context.hh95 using VecRegContainer = TheISA::VecRegContainer;
213 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
214 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
257 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
333 virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
334 virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
335 virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
H A Dexec_context.hh77 using VecRegContainer = TheISA::VecRegContainer;
117 virtual const VecRegContainer&
121 virtual VecRegContainer&
127 const VecRegContainer& val) = 0;
H A Dsimple_thread.hh99 using VecRegContainer = TheISA::VecRegContainer;
108 VecRegContainer vecRegs[TheISA::NumVecRegs];
306 const VecRegContainer&
311 const VecRegContainer& regVal = readVecRegFlat(flatIndex);
317 VecRegContainer&
322 VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
482 setVecReg(const RegId &reg, const VecRegContainer &val) override
620 const VecRegContainer &
626 VecRegContainer
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H A Dthread_context.cc84 const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
85 const TheISA::VecRegContainer& t2 = two->readVecReg(rid);
177 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
218 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
H A Dbase_dyn_inst.hh84 using VecRegContainer = TheISA::VecRegContainer;
684 const VecRegContainer& val)
/gem5/src/arch/sparc/
H A Dregisters.hh53 using VecRegContainer = ::DummyVecRegContainer;
/gem5/src/cpu/o3/
H A Dregfile.hh68 using VecRegContainer = TheISA::VecRegContainer;
87 std::vector<VecRegContainer> vectorRegFile;
208 const VecRegContainer &
221 VecRegContainer &
225 return const_cast<VecRegContainer&>(readVecReg(phys_reg));
330 setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
H A Dthread_context.hh210 const VecRegContainer &
219 VecRegContainer &
326 setVecReg(const RegId& reg, const VecRegContainer& val) override
456 const VecRegContainer& readVecRegFlat(RegIndex idx) const override;
458 VecRegContainer& getWritableVecRegFlat(RegIndex idx) override;
459 void setVecRegFlat(RegIndex idx, const VecRegContainer& val) override;
H A Dcpu.hh107 using VecRegContainer = TheISA::VecRegContainer;
359 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
364 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
416 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
428 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
430 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
475 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
H A Ddyn_inst.hh69 using VecRegContainer = TheISA::VecRegContainer;
282 const VecRegContainer&
291 VecRegContainer&
402 const VecRegContainer& val) override
H A Dthread_context_impl.hh221 const TheISA::VecRegContainer&
228 TheISA::VecRegContainer&
284 RegIndex reg_idx, const VecRegContainer& val)
H A Drename_map.cc205 TheISA::VecRegContainer new_RF[TheISA::NumVecRegs];
/gem5/src/arch/power/
H A Dregisters.hh53 using VecRegContainer = ::DummyVecRegContainer;
/gem5/src/arch/x86/
H A Dregisters.hh103 using VecRegContainer = ::DummyVecRegContainer;
/gem5/src/sim/
H A Dinsttracer.hh100 ::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec;
201 setData(::VecRegContainer<TheISA::VecRegSizeBytes>& d)
203 data.as_vec = new ::VecRegContainer<TheISA::VecRegSizeBytes>(d);
/gem5/src/arch/alpha/
H A Dregisters.hh53 using VecRegContainer = ::DummyVecRegContainer;
/gem5/src/arch/arm/
H A Dregisters.hh73 using VecRegContainer = VecReg::Container;
/gem5/src/cpu/checker/
H A Dthread_context.hh250 const VecRegContainer &
259 VecRegContainer &
361 setVecReg(const RegId& reg, const VecRegContainer& val) override
502 const VecRegContainer &
511 VecRegContainer &
518 setVecRegFlat(RegIndex idx, const VecRegContainer& val) override
H A Dcpu.hh91 using VecRegContainer = TheISA::VecRegContainer;
210 const VecRegContainer &
221 VecRegContainer &
394 const VecRegContainer& val) override
/gem5/src/cpu/simple/
H A Dexec_context.hh63 using VecRegContainer = TheISA::VecRegContainer;
219 const VecRegContainer &
229 VecRegContainer &
241 const VecRegContainer& val) override
/gem5/src/arch/mips/
H A Dregisters.hh290 using VecRegContainer = ::DummyVecRegContainer;
/gem5/src/cpu/minor/
H A Dexec_context.hh159 const TheISA::VecRegContainer &
167 TheISA::VecRegContainer &
217 const TheISA::VecRegContainer& val) override

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