11689SN/A/* 214025Sgiacomo.gabrielli@arm.com * Copyright (c) 2016-2018 ARM Limited 312109SRekai.GonzalezAlberquilla@arm.com * All rights reserved 412109SRekai.GonzalezAlberquilla@arm.com * 512109SRekai.GonzalezAlberquilla@arm.com * The license below extends only to copyright in the software and shall 612109SRekai.GonzalezAlberquilla@arm.com * not be construed as granting a license to any other intellectual 712109SRekai.GonzalezAlberquilla@arm.com * property including but not limited to intellectual property relating 812109SRekai.GonzalezAlberquilla@arm.com * to a hardware implementation of the functionality of the software 912109SRekai.GonzalezAlberquilla@arm.com * licensed hereunder. You may use the software subject to the license 1012109SRekai.GonzalezAlberquilla@arm.com * terms below provided that you ensure that this notice is replicated 1112109SRekai.GonzalezAlberquilla@arm.com * unmodified and in its entirety in all distributions of the software, 1212109SRekai.GonzalezAlberquilla@arm.com * modified or unmodified, in source code or in binary form. 1312109SRekai.GonzalezAlberquilla@arm.com * 141689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 159915Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422665Ssaidi@eecs.umich.edu * Gabe Black 431689SN/A */ 441689SN/A 452292SN/A#ifndef __CPU_O3_REGFILE_HH__ 462292SN/A#define __CPU_O3_REGFILE_HH__ 471060SN/A 486658Snate@binkert.org#include <vector> 496658Snate@binkert.org 502165SN/A#include "arch/isa_traits.hh" 512669Sktlim@umich.edu#include "arch/types.hh" 521681SN/A#include "base/trace.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 541717SN/A#include "cpu/o3/comm.hh" 558232Snate@binkert.org#include "debug/IEW.hh" 5612109SRekai.GonzalezAlberquilla@arm.com#include "enums/VecRegRenameMode.hh" 571060SN/A 589919Ssteve.reinhardt@amd.comclass UnifiedFreeList; 599919Ssteve.reinhardt@amd.com 602292SN/A/** 612292SN/A * Simple physical register file class. 622292SN/A */ 631060SN/Aclass PhysRegFile 641060SN/A{ 659915Ssteve.reinhardt@amd.com private: 669915Ssteve.reinhardt@amd.com 6712109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 6812109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 6912109SRekai.GonzalezAlberquilla@arm.com using PhysIds = std::vector<PhysRegId>; 7012109SRekai.GonzalezAlberquilla@arm.com using VecMode = Enums::VecRegRenameMode; 7113610Sgiacomo.gabrielli@arm.com using VecPredRegContainer = TheISA::VecPredRegContainer; 7212109SRekai.GonzalezAlberquilla@arm.com public: 7314025Sgiacomo.gabrielli@arm.com using IdRange = std::pair<PhysIds::iterator, 7414025Sgiacomo.gabrielli@arm.com PhysIds::iterator>; 7512109SRekai.GonzalezAlberquilla@arm.com private: 7612109SRekai.GonzalezAlberquilla@arm.com static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; 772159SN/A 789915Ssteve.reinhardt@amd.com /** Integer register file. */ 7913557Sgabeblack@google.com std::vector<RegVal> intRegFile; 8012105Snathanael.premillieu@arm.com std::vector<PhysRegId> intRegIds; 811060SN/A 829915Ssteve.reinhardt@amd.com /** Floating point register file. */ 8313557Sgabeblack@google.com std::vector<RegVal> floatRegFile; 8412105Snathanael.premillieu@arm.com std::vector<PhysRegId> floatRegIds; 859915Ssteve.reinhardt@amd.com 8612109SRekai.GonzalezAlberquilla@arm.com /** Vector register file. */ 8712109SRekai.GonzalezAlberquilla@arm.com std::vector<VecRegContainer> vectorRegFile; 8812109SRekai.GonzalezAlberquilla@arm.com std::vector<PhysRegId> vecRegIds; 8912109SRekai.GonzalezAlberquilla@arm.com std::vector<PhysRegId> vecElemIds; 9012109SRekai.GonzalezAlberquilla@arm.com 9113610Sgiacomo.gabrielli@arm.com /** Predicate register file. */ 9213610Sgiacomo.gabrielli@arm.com std::vector<VecPredRegContainer> vecPredRegFile; 9313610Sgiacomo.gabrielli@arm.com std::vector<PhysRegId> vecPredRegIds; 9413610Sgiacomo.gabrielli@arm.com 959920Syasuko.eckert@amd.com /** Condition-code register file. */ 9613622Sgabeblack@google.com std::vector<RegVal> ccRegFile; 9712105Snathanael.premillieu@arm.com std::vector<PhysRegId> ccRegIds; 9812105Snathanael.premillieu@arm.com 9912105Snathanael.premillieu@arm.com /** Misc Reg Ids */ 10012105Snathanael.premillieu@arm.com std::vector<PhysRegId> miscRegIds; 1019920Syasuko.eckert@amd.com 1029915Ssteve.reinhardt@amd.com /** 10312105Snathanael.premillieu@arm.com * Number of physical general purpose registers 1049915Ssteve.reinhardt@amd.com */ 10512105Snathanael.premillieu@arm.com unsigned numPhysicalIntRegs; 1069915Ssteve.reinhardt@amd.com 1079920Syasuko.eckert@amd.com /** 10812109SRekai.GonzalezAlberquilla@arm.com * Number of physical floating point registers 1099920Syasuko.eckert@amd.com */ 11012105Snathanael.premillieu@arm.com unsigned numPhysicalFloatRegs; 11112105Snathanael.premillieu@arm.com 11212105Snathanael.premillieu@arm.com /** 11312109SRekai.GonzalezAlberquilla@arm.com * Number of physical vector registers 11412109SRekai.GonzalezAlberquilla@arm.com */ 11512109SRekai.GonzalezAlberquilla@arm.com unsigned numPhysicalVecRegs; 11612109SRekai.GonzalezAlberquilla@arm.com 11712109SRekai.GonzalezAlberquilla@arm.com /** 11812109SRekai.GonzalezAlberquilla@arm.com * Number of physical vector element registers 11912109SRekai.GonzalezAlberquilla@arm.com */ 12012109SRekai.GonzalezAlberquilla@arm.com unsigned numPhysicalVecElemRegs; 12112109SRekai.GonzalezAlberquilla@arm.com 12212109SRekai.GonzalezAlberquilla@arm.com /** 12313610Sgiacomo.gabrielli@arm.com * Number of physical predicate registers 12413610Sgiacomo.gabrielli@arm.com */ 12513610Sgiacomo.gabrielli@arm.com unsigned numPhysicalVecPredRegs; 12613610Sgiacomo.gabrielli@arm.com 12713610Sgiacomo.gabrielli@arm.com /** 12812109SRekai.GonzalezAlberquilla@arm.com * Number of physical CC registers 12912105Snathanael.premillieu@arm.com */ 13012105Snathanael.premillieu@arm.com unsigned numPhysicalCCRegs; 1319920Syasuko.eckert@amd.com 1329915Ssteve.reinhardt@amd.com /** Total number of physical registers. */ 1339915Ssteve.reinhardt@amd.com unsigned totalNumRegs; 1349915Ssteve.reinhardt@amd.com 13512109SRekai.GonzalezAlberquilla@arm.com /** Mode in which vector registers are addressed. */ 13612109SRekai.GonzalezAlberquilla@arm.com VecMode vecMode; 13712109SRekai.GonzalezAlberquilla@arm.com 1381060SN/A public: 1392292SN/A /** 1402292SN/A * Constructs a physical register file with the specified amount of 1412292SN/A * integer and floating point registers. 1422292SN/A */ 1439915Ssteve.reinhardt@amd.com PhysRegFile(unsigned _numPhysicalIntRegs, 1449920Syasuko.eckert@amd.com unsigned _numPhysicalFloatRegs, 14512109SRekai.GonzalezAlberquilla@arm.com unsigned _numPhysicalVecRegs, 14613610Sgiacomo.gabrielli@arm.com unsigned _numPhysicalVecPredRegs, 14712109SRekai.GonzalezAlberquilla@arm.com unsigned _numPhysicalCCRegs, 14812109SRekai.GonzalezAlberquilla@arm.com VecMode vmode 14912109SRekai.GonzalezAlberquilla@arm.com ); 1501060SN/A 1519086Sandreas.hansson@arm.com /** 1529086Sandreas.hansson@arm.com * Destructor to free resources 1539086Sandreas.hansson@arm.com */ 1549919Ssteve.reinhardt@amd.com ~PhysRegFile() {} 1559919Ssteve.reinhardt@amd.com 1569919Ssteve.reinhardt@amd.com /** Initialize the free list */ 1579919Ssteve.reinhardt@amd.com void initFreeList(UnifiedFreeList *freeList); 1589086Sandreas.hansson@arm.com 1599915Ssteve.reinhardt@amd.com /** @return the number of integer physical registers. */ 16012105Snathanael.premillieu@arm.com unsigned numIntPhysRegs() const { return numPhysicalIntRegs; } 1619915Ssteve.reinhardt@amd.com 1629915Ssteve.reinhardt@amd.com /** @return the number of floating-point physical registers. */ 16312105Snathanael.premillieu@arm.com unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; } 16412109SRekai.GonzalezAlberquilla@arm.com /** @return the number of vector physical registers. */ 16512109SRekai.GonzalezAlberquilla@arm.com unsigned numVecPhysRegs() const { return numPhysicalVecRegs; } 16613610Sgiacomo.gabrielli@arm.com /** @return the number of predicate physical registers. */ 16713610Sgiacomo.gabrielli@arm.com unsigned numPredPhysRegs() const { return numPhysicalVecPredRegs; } 16812109SRekai.GonzalezAlberquilla@arm.com 16912109SRekai.GonzalezAlberquilla@arm.com /** @return the number of vector physical registers. */ 17012109SRekai.GonzalezAlberquilla@arm.com unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; } 1719920Syasuko.eckert@amd.com 1729920Syasuko.eckert@amd.com /** @return the number of condition-code physical registers. */ 17312105Snathanael.premillieu@arm.com unsigned numCCPhysRegs() const { return numPhysicalCCRegs; } 1749915Ssteve.reinhardt@amd.com 1759915Ssteve.reinhardt@amd.com /** @return the total number of physical registers. */ 1769915Ssteve.reinhardt@amd.com unsigned totalNumPhysRegs() const { return totalNumRegs; } 1779915Ssteve.reinhardt@amd.com 17812105Snathanael.premillieu@arm.com /** Gets a misc register PhysRegIdPtr. */ 17912105Snathanael.premillieu@arm.com PhysRegIdPtr getMiscRegId(RegIndex reg_idx) { 18012105Snathanael.premillieu@arm.com return &miscRegIds[reg_idx]; 1819915Ssteve.reinhardt@amd.com } 1821060SN/A 1832292SN/A /** Reads an integer register. */ 18413557Sgabeblack@google.com RegVal 18513557Sgabeblack@google.com readIntReg(PhysRegIdPtr phys_reg) const 1861060SN/A { 18712105Snathanael.premillieu@arm.com assert(phys_reg->isIntPhysReg()); 1881061SN/A 1891060SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 19012106SRekai.GonzalezAlberquilla@arm.com "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]); 19112106SRekai.GonzalezAlberquilla@arm.com return intRegFile[phys_reg->index()]; 1921060SN/A } 1931060SN/A 19413557Sgabeblack@google.com RegVal 19513611Sgabeblack@google.com readFloatReg(PhysRegIdPtr phys_reg) const 1962455SN/A { 19712105Snathanael.premillieu@arm.com assert(phys_reg->isFloatPhysReg()); 1989915Ssteve.reinhardt@amd.com 19913557Sgabeblack@google.com RegVal floatRegBits = floatRegFile[phys_reg->index()]; 2002455SN/A 2012455SN/A DPRINTF(IEW, "RegFile: Access to float register %i as int, " 20213557Sgabeblack@google.com "has data %#x\n", phys_reg->index(), floatRegBits); 2032455SN/A 2042455SN/A return floatRegBits; 2051060SN/A } 2061060SN/A 20712109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register. */ 20813557Sgabeblack@google.com const VecRegContainer & 20913557Sgabeblack@google.com readVecReg(PhysRegIdPtr phys_reg) const 21012109SRekai.GonzalezAlberquilla@arm.com { 21112109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysReg()); 21212109SRekai.GonzalezAlberquilla@arm.com 21312109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Access to vector register %i, has " 21412109SRekai.GonzalezAlberquilla@arm.com "data %s\n", int(phys_reg->index()), 21513610Sgiacomo.gabrielli@arm.com vectorRegFile[phys_reg->index()].print()); 21612109SRekai.GonzalezAlberquilla@arm.com 21712109SRekai.GonzalezAlberquilla@arm.com return vectorRegFile[phys_reg->index()]; 21812109SRekai.GonzalezAlberquilla@arm.com } 21912109SRekai.GonzalezAlberquilla@arm.com 22012109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register for modification. */ 22113557Sgabeblack@google.com VecRegContainer & 22213557Sgabeblack@google.com getWritableVecReg(PhysRegIdPtr phys_reg) 22312109SRekai.GonzalezAlberquilla@arm.com { 22412109SRekai.GonzalezAlberquilla@arm.com /* const_cast for not duplicating code above. */ 22512109SRekai.GonzalezAlberquilla@arm.com return const_cast<VecRegContainer&>(readVecReg(phys_reg)); 22612109SRekai.GonzalezAlberquilla@arm.com } 22712109SRekai.GonzalezAlberquilla@arm.com 22812109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register lane. */ 22912109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem, int LaneIdx> 23012109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 23112109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 23212109SRekai.GonzalezAlberquilla@arm.com { 23312109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg).laneView<VecElem, LaneIdx>(); 23412109SRekai.GonzalezAlberquilla@arm.com } 23512109SRekai.GonzalezAlberquilla@arm.com 23612109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register lane. */ 23712109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem> 23812109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 23912109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 24012109SRekai.GonzalezAlberquilla@arm.com { 24112109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex()); 24212109SRekai.GonzalezAlberquilla@arm.com } 24312109SRekai.GonzalezAlberquilla@arm.com 24412109SRekai.GonzalezAlberquilla@arm.com /** Get a vector register lane for modification. */ 24512109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 24612109SRekai.GonzalezAlberquilla@arm.com void 24712109SRekai.GonzalezAlberquilla@arm.com setVecLane(PhysRegIdPtr phys_reg, const LD& val) 24812109SRekai.GonzalezAlberquilla@arm.com { 24912109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysReg()); 25012109SRekai.GonzalezAlberquilla@arm.com 25112109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n", 25212109SRekai.GonzalezAlberquilla@arm.com int(phys_reg->index()), phys_reg->elemIndex(), val); 25312109SRekai.GonzalezAlberquilla@arm.com 25412109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>( 25512109SRekai.GonzalezAlberquilla@arm.com phys_reg->elemIndex()) = val; 25612109SRekai.GonzalezAlberquilla@arm.com } 25712109SRekai.GonzalezAlberquilla@arm.com 25812109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector element. */ 25913557Sgabeblack@google.com const VecElem & 26013557Sgabeblack@google.com readVecElem(PhysRegIdPtr phys_reg) const 26112109SRekai.GonzalezAlberquilla@arm.com { 26212109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysElem()); 26312109SRekai.GonzalezAlberquilla@arm.com auto ret = vectorRegFile[phys_reg->index()].as<VecElem>(); 26412109SRekai.GonzalezAlberquilla@arm.com const VecElem& val = ret[phys_reg->elemIndex()]; 26512109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Access to element %d of vector register %i," 26612109SRekai.GonzalezAlberquilla@arm.com " has data %#x\n", phys_reg->elemIndex(), 26712109SRekai.GonzalezAlberquilla@arm.com int(phys_reg->index()), val); 26812109SRekai.GonzalezAlberquilla@arm.com 26912109SRekai.GonzalezAlberquilla@arm.com return val; 27012109SRekai.GonzalezAlberquilla@arm.com } 27112109SRekai.GonzalezAlberquilla@arm.com 27213610Sgiacomo.gabrielli@arm.com /** Reads a predicate register. */ 27313610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readVecPredReg(PhysRegIdPtr phys_reg) const 27413610Sgiacomo.gabrielli@arm.com { 27513610Sgiacomo.gabrielli@arm.com assert(phys_reg->isVecPredPhysReg()); 27613610Sgiacomo.gabrielli@arm.com 27713610Sgiacomo.gabrielli@arm.com DPRINTF(IEW, "RegFile: Access to predicate register %i, has " 27813610Sgiacomo.gabrielli@arm.com "data %s\n", int(phys_reg->index()), 27913610Sgiacomo.gabrielli@arm.com vecPredRegFile[phys_reg->index()].print()); 28013610Sgiacomo.gabrielli@arm.com 28113610Sgiacomo.gabrielli@arm.com return vecPredRegFile[phys_reg->index()]; 28213610Sgiacomo.gabrielli@arm.com } 28313610Sgiacomo.gabrielli@arm.com 28413610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr phys_reg) 28513610Sgiacomo.gabrielli@arm.com { 28613610Sgiacomo.gabrielli@arm.com /* const_cast for not duplicating code above. */ 28713610Sgiacomo.gabrielli@arm.com return const_cast<VecPredRegContainer&>(readVecPredReg(phys_reg)); 28813610Sgiacomo.gabrielli@arm.com } 28913610Sgiacomo.gabrielli@arm.com 2909920Syasuko.eckert@amd.com /** Reads a condition-code register. */ 29113622Sgabeblack@google.com RegVal 29213557Sgabeblack@google.com readCCReg(PhysRegIdPtr phys_reg) 2939920Syasuko.eckert@amd.com { 29412105Snathanael.premillieu@arm.com assert(phys_reg->isCCPhysReg()); 2959920Syasuko.eckert@amd.com 2969920Syasuko.eckert@amd.com DPRINTF(IEW, "RegFile: Access to cc register %i, has " 29712106SRekai.GonzalezAlberquilla@arm.com "data %#x\n", phys_reg->index(), 29812106SRekai.GonzalezAlberquilla@arm.com ccRegFile[phys_reg->index()]); 2999920Syasuko.eckert@amd.com 30012106SRekai.GonzalezAlberquilla@arm.com return ccRegFile[phys_reg->index()]; 3019920Syasuko.eckert@amd.com } 3029920Syasuko.eckert@amd.com 3032292SN/A /** Sets an integer register to the given value. */ 30413557Sgabeblack@google.com void 30513557Sgabeblack@google.com setIntReg(PhysRegIdPtr phys_reg, RegVal val) 3061060SN/A { 30712105Snathanael.premillieu@arm.com assert(phys_reg->isIntPhysReg()); 3081061SN/A 3092690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 31012106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), val); 3111060SN/A 31212105Snathanael.premillieu@arm.com if (!phys_reg->isZeroReg()) 31312106SRekai.GonzalezAlberquilla@arm.com intRegFile[phys_reg->index()] = val; 3141060SN/A } 3151060SN/A 31613557Sgabeblack@google.com void 31713611Sgabeblack@google.com setFloatReg(PhysRegIdPtr phys_reg, RegVal val) 3182455SN/A { 31912105Snathanael.premillieu@arm.com assert(phys_reg->isFloatPhysReg()); 3202455SN/A 3212690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 32212106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), (uint64_t)val); 3232455SN/A 32412109SRekai.GonzalezAlberquilla@arm.com if (!phys_reg->isZeroReg()) 32513501Sgabeblack@google.com floatRegFile[phys_reg->index()] = val; 32612109SRekai.GonzalezAlberquilla@arm.com } 32712109SRekai.GonzalezAlberquilla@arm.com 32812109SRekai.GonzalezAlberquilla@arm.com /** Sets a vector register to the given value. */ 32913557Sgabeblack@google.com void 33013557Sgabeblack@google.com setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) 33112109SRekai.GonzalezAlberquilla@arm.com { 33212109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysReg()); 33312109SRekai.GonzalezAlberquilla@arm.com 33412109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n", 33512109SRekai.GonzalezAlberquilla@arm.com int(phys_reg->index()), val.print()); 33612109SRekai.GonzalezAlberquilla@arm.com 33712109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()] = val; 33812109SRekai.GonzalezAlberquilla@arm.com } 33912109SRekai.GonzalezAlberquilla@arm.com 34012109SRekai.GonzalezAlberquilla@arm.com /** Sets a vector register to the given value. */ 34113557Sgabeblack@google.com void 34213557Sgabeblack@google.com setVecElem(PhysRegIdPtr phys_reg, const VecElem val) 34312109SRekai.GonzalezAlberquilla@arm.com { 34412109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysElem()); 34512109SRekai.GonzalezAlberquilla@arm.com 34612109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to" 34712109SRekai.GonzalezAlberquilla@arm.com " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val); 34812109SRekai.GonzalezAlberquilla@arm.com 34912109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] = 35012109SRekai.GonzalezAlberquilla@arm.com val; 3511060SN/A } 3521060SN/A 35313610Sgiacomo.gabrielli@arm.com /** Sets a predicate register to the given value. */ 35413610Sgiacomo.gabrielli@arm.com void setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val) 35513610Sgiacomo.gabrielli@arm.com { 35613610Sgiacomo.gabrielli@arm.com assert(phys_reg->isVecPredPhysReg()); 35713610Sgiacomo.gabrielli@arm.com 35813610Sgiacomo.gabrielli@arm.com DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n", 35913610Sgiacomo.gabrielli@arm.com int(phys_reg->index()), val.print()); 36013610Sgiacomo.gabrielli@arm.com 36113610Sgiacomo.gabrielli@arm.com vecPredRegFile[phys_reg->index()] = val; 36213610Sgiacomo.gabrielli@arm.com } 36313610Sgiacomo.gabrielli@arm.com 3649920Syasuko.eckert@amd.com /** Sets a condition-code register to the given value. */ 36513557Sgabeblack@google.com void 36613622Sgabeblack@google.com setCCReg(PhysRegIdPtr phys_reg, RegVal val) 3679920Syasuko.eckert@amd.com { 36812105Snathanael.premillieu@arm.com assert(phys_reg->isCCPhysReg()); 3699920Syasuko.eckert@amd.com 3709920Syasuko.eckert@amd.com DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n", 37112106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), (uint64_t)val); 3729920Syasuko.eckert@amd.com 37312106SRekai.GonzalezAlberquilla@arm.com ccRegFile[phys_reg->index()] = val; 3749920Syasuko.eckert@amd.com } 37512109SRekai.GonzalezAlberquilla@arm.com 37612109SRekai.GonzalezAlberquilla@arm.com /** Get the PhysRegIds of the elems of a vector register. 37712109SRekai.GonzalezAlberquilla@arm.com * Auxiliary function to transition from Full vector mode to Elem mode. 37812109SRekai.GonzalezAlberquilla@arm.com */ 37912109SRekai.GonzalezAlberquilla@arm.com IdRange getRegElemIds(PhysRegIdPtr reg); 38012109SRekai.GonzalezAlberquilla@arm.com 38112109SRekai.GonzalezAlberquilla@arm.com /** 38212109SRekai.GonzalezAlberquilla@arm.com * Get the PhysRegIds of the elems of all vector registers. 38312109SRekai.GonzalezAlberquilla@arm.com * Auxiliary function to transition from Full vector mode to Elem mode 38412109SRekai.GonzalezAlberquilla@arm.com * and to initialise the rename map. 38512109SRekai.GonzalezAlberquilla@arm.com */ 38612109SRekai.GonzalezAlberquilla@arm.com IdRange getRegIds(RegClass cls); 38712109SRekai.GonzalezAlberquilla@arm.com 38813557Sgabeblack@google.com /** 38913557Sgabeblack@google.com * Get the true physical register id. 39013557Sgabeblack@google.com * As many parts work with PhysRegIdPtr, we need to be able to produce 39113557Sgabeblack@google.com * the pointer out of just class and register idx. 39213557Sgabeblack@google.com */ 39313557Sgabeblack@google.com PhysRegIdPtr getTrueId(PhysRegIdPtr reg); 3941060SN/A}; 3951060SN/A 3969915Ssteve.reinhardt@amd.com 3979915Ssteve.reinhardt@amd.com#endif //__CPU_O3_REGFILE_HH__ 398