12817Sksewell@umich.edu/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 162817Sksewell@umich.edu * All rights reserved. 172817Sksewell@umich.edu * 182817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272817Sksewell@umich.edu * this software without specific prior written permission. 282817Sksewell@umich.edu * 292817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402817Sksewell@umich.edu * 412817Sksewell@umich.edu * Authors: Kevin Lim 422817Sksewell@umich.edu */ 432817Sksewell@umich.edu 442817Sksewell@umich.edu#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 452817Sksewell@umich.edu#define __CPU_O3_THREAD_CONTEXT_HH__ 462817Sksewell@umich.edu 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 492935Sksewell@umich.edu#include "cpu/thread_context.hh" 502817Sksewell@umich.edu 512834Sksewell@umich.educlass EndQuiesceEvent; 522834Sksewell@umich.edunamespace Kernel { 532834Sksewell@umich.edu class Statistics; 548902Sandreas.hansson@arm.com} 552834Sksewell@umich.edu 562817Sksewell@umich.edu/** 572817Sksewell@umich.edu * Derived ThreadContext class for use with the O3CPU. It 582817Sksewell@umich.edu * provides the interface for any external objects to access a 592817Sksewell@umich.edu * single thread's state and some general CPU state. Any time 602817Sksewell@umich.edu * external objects try to update state through this interface, 612817Sksewell@umich.edu * the CPU will create an event to squash all in-flight 622817Sksewell@umich.edu * instructions in order to ensure state is maintained correctly. 632817Sksewell@umich.edu * It must be defined specifically for the O3CPU because 642817Sksewell@umich.edu * not all architectural state is located within the O3ThreadState 652817Sksewell@umich.edu * (such as the commit PC, and registers), and specific actions 662817Sksewell@umich.edu * must be taken when using this interface (such as squashing all 672817Sksewell@umich.edu * in-flight instructions when doing a write to this interface). 682817Sksewell@umich.edu */ 692817Sksewell@umich.edutemplate <class Impl> 702817Sksewell@umich.educlass O3ThreadContext : public ThreadContext 712817Sksewell@umich.edu{ 722817Sksewell@umich.edu public: 732817Sksewell@umich.edu typedef typename Impl::O3CPU O3CPU; 742817Sksewell@umich.edu 752817Sksewell@umich.edu /** Pointer to the CPU. */ 762817Sksewell@umich.edu O3CPU *cpu; 772817Sksewell@umich.edu 782817Sksewell@umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 792817Sksewell@umich.edu O3ThreadState<Impl> *thread; 802817Sksewell@umich.edu 813784Sgblack@eecs.umich.edu /** Returns a pointer to the ITB. */ 8213628SAndrea.Mondelli@ucf.edu BaseTLB *getITBPtr() override { return cpu->itb; } 833784Sgblack@eecs.umich.edu 843784Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 8513628SAndrea.Mondelli@ucf.edu BaseTLB *getDTBPtr() override { return cpu->dtb; } 863784Sgblack@eecs.umich.edu 8713628SAndrea.Mondelli@ucf.edu CheckerCPU *getCheckerCpuPtr() override { return NULL; } 888733Sgeoffrey.blake@arm.com 8913693Sgiacomo.gabrielli@arm.com TheISA::ISA * 9013693Sgiacomo.gabrielli@arm.com getIsaPtr() override 9113693Sgiacomo.gabrielli@arm.com { 9213693Sgiacomo.gabrielli@arm.com return cpu->isa[thread->threadId()]; 9313693Sgiacomo.gabrielli@arm.com } 9413693Sgiacomo.gabrielli@arm.com 959023Sgblack@eecs.umich.edu TheISA::Decoder * 9613628SAndrea.Mondelli@ucf.edu getDecoderPtr() override 979023Sgblack@eecs.umich.edu { 989023Sgblack@eecs.umich.edu return cpu->fetch.decoder[thread->threadId()]; 999023Sgblack@eecs.umich.edu } 1008541Sgblack@eecs.umich.edu 1012817Sksewell@umich.edu /** Returns a pointer to this CPU. */ 10213865Sgabeblack@google.com BaseCPU *getCpuPtr() override { return cpu; } 1032817Sksewell@umich.edu 1042817Sksewell@umich.edu /** Reads this CPU's ID. */ 10513865Sgabeblack@google.com int cpuId() const override { return cpu->cpuId(); } 1062817Sksewell@umich.edu 10710190Sakash.bagdia@arm.com /** Reads this CPU's Socket ID. */ 10813865Sgabeblack@google.com uint32_t socketId() const override { return cpu->socketId(); } 10910190Sakash.bagdia@arm.com 11013865Sgabeblack@google.com ContextID contextId() const override { return thread->contextId(); } 1115714Shsul@eecs.umich.edu 11213865Sgabeblack@google.com void setContextId(ContextID id) override { thread->setContextId(id); } 1135714Shsul@eecs.umich.edu 1145715Shsul@eecs.umich.edu /** Returns this thread's ID number. */ 11513865Sgabeblack@google.com int threadId() const override { return thread->threadId(); } 11613865Sgabeblack@google.com void setThreadId(int id) override { return thread->setThreadId(id); } 1175715Shsul@eecs.umich.edu 1182817Sksewell@umich.edu /** Returns a pointer to the system. */ 11913865Sgabeblack@google.com System *getSystemPtr() override { return cpu->system; } 1202817Sksewell@umich.edu 1212817Sksewell@umich.edu /** Returns a pointer to this thread's kernel statistics. */ 12213905Sgabeblack@google.com ::Kernel::Statistics * 12313865Sgabeblack@google.com getKernelStats() override 12413865Sgabeblack@google.com { 12513865Sgabeblack@google.com return thread->kernelStats; 12613865Sgabeblack@google.com } 1272817Sksewell@umich.edu 1288541Sgblack@eecs.umich.edu /** Returns a pointer to this thread's process. */ 12913865Sgabeblack@google.com Process *getProcessPtr() override { return thread->getProcessPtr(); } 1308754Sgblack@eecs.umich.edu 13113865Sgabeblack@google.com void setProcessPtr(Process *p) override { thread->setProcessPtr(p); } 13211886Sbrandon.potter@amd.com 13313865Sgabeblack@google.com PortProxy &getPhysProxy() override { return thread->getPhysProxy(); } 1342817Sksewell@umich.edu 13514022Sgabeblack@google.com PortProxy &getVirtProxy() override; 1363675Sktlim@umich.edu 13713865Sgabeblack@google.com void 13813865Sgabeblack@google.com initMemProxies(ThreadContext *tc) override 13913865Sgabeblack@google.com { 14013865Sgabeblack@google.com thread->initMemProxies(tc); 14113865Sgabeblack@google.com } 1428799Sgblack@eecs.umich.edu 1432817Sksewell@umich.edu /** Returns this thread's status. */ 14413865Sgabeblack@google.com Status status() const override { return thread->status(); } 1452817Sksewell@umich.edu 1462817Sksewell@umich.edu /** Sets this thread's status. */ 14713865Sgabeblack@google.com void 14813865Sgabeblack@google.com setStatus(Status new_status) override 14913865Sgabeblack@google.com { 15013865Sgabeblack@google.com thread->setStatus(new_status); 15113865Sgabeblack@google.com } 1522817Sksewell@umich.edu 15310407Smitch.hayenga@arm.com /** Set the status to Active. */ 15413865Sgabeblack@google.com void activate() override; 1552817Sksewell@umich.edu 1562817Sksewell@umich.edu /** Set the status to Suspended. */ 15713865Sgabeblack@google.com void suspend() override; 1582817Sksewell@umich.edu 1592817Sksewell@umich.edu /** Set the status to Halted. */ 16013865Sgabeblack@google.com void halt() override; 1612817Sksewell@umich.edu 1622817Sksewell@umich.edu /** Dumps the function profiling information. 1632817Sksewell@umich.edu * @todo: Implement. 1642817Sksewell@umich.edu */ 16513865Sgabeblack@google.com void dumpFuncProfile() override; 1668777Sgblack@eecs.umich.edu 1672817Sksewell@umich.edu /** Takes over execution of a thread from another CPU. */ 16813865Sgabeblack@google.com void takeOverFrom(ThreadContext *old_context) override; 1692817Sksewell@umich.edu 1702817Sksewell@umich.edu /** Registers statistics associated with this TC. */ 17113865Sgabeblack@google.com void regStats(const std::string &name) override; 1722817Sksewell@umich.edu 1732817Sksewell@umich.edu /** Reads the last tick that this thread was activated on. */ 17413865Sgabeblack@google.com Tick readLastActivate() override; 1752817Sksewell@umich.edu /** Reads the last tick that this thread was suspended on. */ 17613865Sgabeblack@google.com Tick readLastSuspend() override; 1772817Sksewell@umich.edu 1782817Sksewell@umich.edu /** Clears the function profiling information. */ 17913865Sgabeblack@google.com void profileClear() override; 1802817Sksewell@umich.edu /** Samples the function profiling information. */ 18113865Sgabeblack@google.com void profileSample() override; 1822817Sksewell@umich.edu 1832817Sksewell@umich.edu /** Copies the architectural registers from another TC into this TC. */ 18413865Sgabeblack@google.com void copyArchRegs(ThreadContext *tc) override; 1852817Sksewell@umich.edu 1862817Sksewell@umich.edu /** Resets all architectural registers to 0. */ 18713865Sgabeblack@google.com void clearArchRegs() override; 1882817Sksewell@umich.edu 1892817Sksewell@umich.edu /** Reads an integer register. */ 19013865Sgabeblack@google.com RegVal 19113865Sgabeblack@google.com readReg(RegIndex reg_idx) 19213557Sgabeblack@google.com { 19312106SRekai.GonzalezAlberquilla@arm.com return readIntRegFlat(flattenRegId(RegId(IntRegClass, 19412106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 19512106SRekai.GonzalezAlberquilla@arm.com } 19613865Sgabeblack@google.com RegVal 19713865Sgabeblack@google.com readIntReg(RegIndex reg_idx) const override 19813557Sgabeblack@google.com { 19912106SRekai.GonzalezAlberquilla@arm.com return readIntRegFlat(flattenRegId(RegId(IntRegClass, 20012106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 2019426SAndreas.Sandberg@ARM.com } 2022817Sksewell@umich.edu 20313865Sgabeblack@google.com RegVal 20413865Sgabeblack@google.com readFloatReg(RegIndex reg_idx) const override 20513557Sgabeblack@google.com { 20613611Sgabeblack@google.com return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, 20713611Sgabeblack@google.com reg_idx)).index()); 2089426SAndreas.Sandberg@ARM.com } 2092817Sksewell@umich.edu 21013865Sgabeblack@google.com const VecRegContainer & 21113628SAndrea.Mondelli@ucf.edu readVecReg(const RegId& id) const override 21213557Sgabeblack@google.com { 21312109SRekai.GonzalezAlberquilla@arm.com return readVecRegFlat(flattenRegId(id).index()); 21412109SRekai.GonzalezAlberquilla@arm.com } 21512109SRekai.GonzalezAlberquilla@arm.com 21612109SRekai.GonzalezAlberquilla@arm.com /** 21712109SRekai.GonzalezAlberquilla@arm.com * Read vector register operand for modification, hierarchical indexing. 21812109SRekai.GonzalezAlberquilla@arm.com */ 21913865Sgabeblack@google.com VecRegContainer & 22013628SAndrea.Mondelli@ucf.edu getWritableVecReg(const RegId& id) override 22113557Sgabeblack@google.com { 22212109SRekai.GonzalezAlberquilla@arm.com return getWritableVecRegFlat(flattenRegId(id).index()); 22312109SRekai.GonzalezAlberquilla@arm.com } 22412109SRekai.GonzalezAlberquilla@arm.com 22512109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 22612109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 22712109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 22813865Sgabeblack@google.com ConstVecLane8 22913628SAndrea.Mondelli@ucf.edu readVec8BitLaneReg(const RegId& id) const override 23012109SRekai.GonzalezAlberquilla@arm.com { 23112109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint8_t>(flattenRegId(id).index(), 23212109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 23312109SRekai.GonzalezAlberquilla@arm.com } 23412109SRekai.GonzalezAlberquilla@arm.com 23512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 23613865Sgabeblack@google.com ConstVecLane16 23713628SAndrea.Mondelli@ucf.edu readVec16BitLaneReg(const RegId& id) const override 23812109SRekai.GonzalezAlberquilla@arm.com { 23912109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint16_t>(flattenRegId(id).index(), 24012109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 24112109SRekai.GonzalezAlberquilla@arm.com } 24212109SRekai.GonzalezAlberquilla@arm.com 24312109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 24413865Sgabeblack@google.com ConstVecLane32 24513628SAndrea.Mondelli@ucf.edu readVec32BitLaneReg(const RegId& id) const override 24612109SRekai.GonzalezAlberquilla@arm.com { 24712109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint32_t>(flattenRegId(id).index(), 24812109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 24912109SRekai.GonzalezAlberquilla@arm.com } 25012109SRekai.GonzalezAlberquilla@arm.com 25112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 25213865Sgabeblack@google.com ConstVecLane64 25313628SAndrea.Mondelli@ucf.edu readVec64BitLaneReg(const RegId& id) const override 25412109SRekai.GonzalezAlberquilla@arm.com { 25512109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint64_t>(flattenRegId(id).index(), 25612109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 25712109SRekai.GonzalezAlberquilla@arm.com } 25812109SRekai.GonzalezAlberquilla@arm.com 25912109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 26013865Sgabeblack@google.com void 26113865Sgabeblack@google.com setVecLane(const RegId& reg, 26213865Sgabeblack@google.com const LaneData<LaneSize::Byte>& val) override 26313865Sgabeblack@google.com { 26413865Sgabeblack@google.com return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 26513865Sgabeblack@google.com } 26613865Sgabeblack@google.com void 26713865Sgabeblack@google.com setVecLane(const RegId& reg, 26813865Sgabeblack@google.com const LaneData<LaneSize::TwoByte>& val) override 26913865Sgabeblack@google.com { 27013865Sgabeblack@google.com return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 27113865Sgabeblack@google.com } 27213865Sgabeblack@google.com void 27313865Sgabeblack@google.com setVecLane(const RegId& reg, 27413865Sgabeblack@google.com const LaneData<LaneSize::FourByte>& val) override 27513865Sgabeblack@google.com { 27613865Sgabeblack@google.com return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 27713865Sgabeblack@google.com } 27813865Sgabeblack@google.com void 27913865Sgabeblack@google.com setVecLane(const RegId& reg, 28013865Sgabeblack@google.com const LaneData<LaneSize::EightByte>& val) override 28113865Sgabeblack@google.com { 28213865Sgabeblack@google.com return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 28313865Sgabeblack@google.com } 28412109SRekai.GonzalezAlberquilla@arm.com /** @} */ 28512109SRekai.GonzalezAlberquilla@arm.com 28613865Sgabeblack@google.com const VecElem & 28713865Sgabeblack@google.com readVecElem(const RegId& reg) const override 28813865Sgabeblack@google.com { 28912109SRekai.GonzalezAlberquilla@arm.com return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex()); 29012109SRekai.GonzalezAlberquilla@arm.com } 29112109SRekai.GonzalezAlberquilla@arm.com 29213865Sgabeblack@google.com const VecPredRegContainer & 29313865Sgabeblack@google.com readVecPredReg(const RegId& id) const override 29413865Sgabeblack@google.com { 29513610Sgiacomo.gabrielli@arm.com return readVecPredRegFlat(flattenRegId(id).index()); 29613610Sgiacomo.gabrielli@arm.com } 29713610Sgiacomo.gabrielli@arm.com 29813865Sgabeblack@google.com VecPredRegContainer& 29913865Sgabeblack@google.com getWritableVecPredReg(const RegId& id) override 30013865Sgabeblack@google.com { 30113610Sgiacomo.gabrielli@arm.com return getWritableVecPredRegFlat(flattenRegId(id).index()); 30213610Sgiacomo.gabrielli@arm.com } 30313610Sgiacomo.gabrielli@arm.com 30413865Sgabeblack@google.com RegVal 30513865Sgabeblack@google.com readCCReg(RegIndex reg_idx) const override 30613622Sgabeblack@google.com { 30712106SRekai.GonzalezAlberquilla@arm.com return readCCRegFlat(flattenRegId(RegId(CCRegClass, 30812106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 3099920Syasuko.eckert@amd.com } 3109920Syasuko.eckert@amd.com 3112817Sksewell@umich.edu /** Sets an integer register to a value. */ 31213865Sgabeblack@google.com void 31313865Sgabeblack@google.com setIntReg(RegIndex reg_idx, RegVal val) override 31413557Sgabeblack@google.com { 31512106SRekai.GonzalezAlberquilla@arm.com setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); 3169426SAndreas.Sandberg@ARM.com } 3172817Sksewell@umich.edu 31813865Sgabeblack@google.com void 31913865Sgabeblack@google.com setFloatReg(RegIndex reg_idx, RegVal val) override 32013557Sgabeblack@google.com { 32113611Sgabeblack@google.com setFloatRegFlat(flattenRegId(RegId(FloatRegClass, 32213611Sgabeblack@google.com reg_idx)).index(), val); 3239426SAndreas.Sandberg@ARM.com } 3242817Sksewell@umich.edu 32513865Sgabeblack@google.com void 32613628SAndrea.Mondelli@ucf.edu setVecReg(const RegId& reg, const VecRegContainer& val) override 32713557Sgabeblack@google.com { 32812109SRekai.GonzalezAlberquilla@arm.com setVecRegFlat(flattenRegId(reg).index(), val); 32912109SRekai.GonzalezAlberquilla@arm.com } 33012109SRekai.GonzalezAlberquilla@arm.com 33113865Sgabeblack@google.com void 33213628SAndrea.Mondelli@ucf.edu setVecElem(const RegId& reg, const VecElem& val) override 33313557Sgabeblack@google.com { 33412109SRekai.GonzalezAlberquilla@arm.com setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 33512109SRekai.GonzalezAlberquilla@arm.com } 33612109SRekai.GonzalezAlberquilla@arm.com 33713865Sgabeblack@google.com void 33813610Sgiacomo.gabrielli@arm.com setVecPredReg(const RegId& reg, 33913628SAndrea.Mondelli@ucf.edu const VecPredRegContainer& val) override 34013610Sgiacomo.gabrielli@arm.com { 34113610Sgiacomo.gabrielli@arm.com setVecPredRegFlat(flattenRegId(reg).index(), val); 34213610Sgiacomo.gabrielli@arm.com } 34313610Sgiacomo.gabrielli@arm.com 34413865Sgabeblack@google.com void 34513865Sgabeblack@google.com setCCReg(RegIndex reg_idx, RegVal val) override 34613557Sgabeblack@google.com { 34712106SRekai.GonzalezAlberquilla@arm.com setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); 3489920Syasuko.eckert@amd.com } 3499920Syasuko.eckert@amd.com 3507720Sgblack@eecs.umich.edu /** Reads this thread's PC state. */ 35113865Sgabeblack@google.com TheISA::PCState 35213865Sgabeblack@google.com pcState() const override 35313865Sgabeblack@google.com { 35413865Sgabeblack@google.com return cpu->pcState(thread->threadId()); 35513865Sgabeblack@google.com } 3567720Sgblack@eecs.umich.edu 3577720Sgblack@eecs.umich.edu /** Sets this thread's PC state. */ 35813865Sgabeblack@google.com void pcState(const TheISA::PCState &val) override; 3597720Sgblack@eecs.umich.edu 36013865Sgabeblack@google.com void pcStateNoRecord(const TheISA::PCState &val) override; 3618733Sgeoffrey.blake@arm.com 3622817Sksewell@umich.edu /** Reads this thread's PC. */ 36313865Sgabeblack@google.com Addr 36413865Sgabeblack@google.com instAddr() const override 36513865Sgabeblack@google.com { 36613865Sgabeblack@google.com return cpu->instAddr(thread->threadId()); 36713865Sgabeblack@google.com } 3682817Sksewell@umich.edu 3692817Sksewell@umich.edu /** Reads this thread's next PC. */ 37013865Sgabeblack@google.com Addr 37113865Sgabeblack@google.com nextInstAddr() const override 37213865Sgabeblack@google.com { 37313865Sgabeblack@google.com return cpu->nextInstAddr(thread->threadId()); 37413865Sgabeblack@google.com } 3752817Sksewell@umich.edu 3767720Sgblack@eecs.umich.edu /** Reads this thread's next PC. */ 37713865Sgabeblack@google.com MicroPC 37813865Sgabeblack@google.com microPC() const override 37913865Sgabeblack@google.com { 38013865Sgabeblack@google.com return cpu->microPC(thread->threadId()); 38113865Sgabeblack@google.com } 3825259Sksewell@umich.edu 3832817Sksewell@umich.edu /** Reads a miscellaneous register. */ 38413865Sgabeblack@google.com RegVal 38513865Sgabeblack@google.com readMiscRegNoEffect(RegIndex misc_reg) const override 38613865Sgabeblack@google.com { 38713865Sgabeblack@google.com return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); 38813865Sgabeblack@google.com } 3894172Ssaidi@eecs.umich.edu 3904172Ssaidi@eecs.umich.edu /** Reads a misc. register, including any side-effects the 3914172Ssaidi@eecs.umich.edu * read might have as defined by the architecture. */ 39213865Sgabeblack@google.com RegVal 39313865Sgabeblack@google.com readMiscReg(RegIndex misc_reg) override 39413865Sgabeblack@google.com { 39513865Sgabeblack@google.com return cpu->readMiscReg(misc_reg, thread->threadId()); 39613865Sgabeblack@google.com } 3972817Sksewell@umich.edu 3982817Sksewell@umich.edu /** Sets a misc. register. */ 39913865Sgabeblack@google.com void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override; 4002817Sksewell@umich.edu 4012817Sksewell@umich.edu /** Sets a misc. register, including any side-effects the 4022817Sksewell@umich.edu * write might have as defined by the architecture. */ 40313865Sgabeblack@google.com void setMiscReg(RegIndex misc_reg, RegVal val) override; 4042817Sksewell@umich.edu 40513865Sgabeblack@google.com RegId flattenRegId(const RegId& regId) const override; 4066313Sgblack@eecs.umich.edu 4072817Sksewell@umich.edu /** Returns the number of consecutive store conditional failures. */ 4082817Sksewell@umich.edu // @todo: Figure out where these store cond failures should go. 40913865Sgabeblack@google.com unsigned 41013865Sgabeblack@google.com readStCondFailures() const override 41113865Sgabeblack@google.com { 41213865Sgabeblack@google.com return thread->storeCondFailures; 41313865Sgabeblack@google.com } 4142817Sksewell@umich.edu 4152817Sksewell@umich.edu /** Sets the number of consecutive store conditional failures. */ 41613865Sgabeblack@google.com void 41713865Sgabeblack@google.com setStCondFailures(unsigned sc_failures) override 41813865Sgabeblack@google.com { 41913865Sgabeblack@google.com thread->storeCondFailures = sc_failures; 42013865Sgabeblack@google.com } 4212817Sksewell@umich.edu 4222817Sksewell@umich.edu /** Executes a syscall in SE mode. */ 42313865Sgabeblack@google.com void 42413865Sgabeblack@google.com syscall(int64_t callnum, Fault *fault) override 42513865Sgabeblack@google.com { 42613865Sgabeblack@google.com return cpu->syscall(callnum, thread->threadId(), fault); 42713865Sgabeblack@google.com } 4282817Sksewell@umich.edu 4292817Sksewell@umich.edu /** Reads the funcExeInst counter. */ 43013865Sgabeblack@google.com Counter readFuncExeInst() const override { return thread->funcExeInst; } 4318777Sgblack@eecs.umich.edu 4325595Sgblack@eecs.umich.edu /** Returns pointer to the quiesce event. */ 43313865Sgabeblack@google.com EndQuiesceEvent * 43413628SAndrea.Mondelli@ucf.edu getQuiesceEvent() override 4355595Sgblack@eecs.umich.edu { 4365595Sgblack@eecs.umich.edu return this->thread->quiesceEvent; 4375595Sgblack@eecs.umich.edu } 4389382SAli.Saidi@ARM.com /** check if the cpu is currently in state update mode and squash if not. 4399382SAli.Saidi@ARM.com * This function will return true if a trap is pending or if a fault or 4409382SAli.Saidi@ARM.com * similar is currently writing to the thread context and doesn't want 4419382SAli.Saidi@ARM.com * reset all the state (see noSquashFromTC). 4429382SAli.Saidi@ARM.com */ 44313557Sgabeblack@google.com inline void 44413557Sgabeblack@google.com conditionalSquash() 4459382SAli.Saidi@ARM.com { 4469382SAli.Saidi@ARM.com if (!thread->trapPending && !thread->noSquashFromTC) 4479382SAli.Saidi@ARM.com cpu->squashFromTC(thread->threadId()); 4489382SAli.Saidi@ARM.com } 4495595Sgblack@eecs.umich.edu 45013865Sgabeblack@google.com RegVal readIntRegFlat(RegIndex idx) const override; 45113865Sgabeblack@google.com void setIntRegFlat(RegIndex idx, RegVal val) override; 4529426SAndreas.Sandberg@ARM.com 45313865Sgabeblack@google.com RegVal readFloatRegFlat(RegIndex idx) const override; 45413865Sgabeblack@google.com void setFloatRegFlat(RegIndex idx, RegVal val) override; 4559920Syasuko.eckert@amd.com 45613865Sgabeblack@google.com const VecRegContainer& readVecRegFlat(RegIndex idx) const override; 45712109SRekai.GonzalezAlberquilla@arm.com /** Read vector register operand for modification, flat indexing. */ 45813865Sgabeblack@google.com VecRegContainer& getWritableVecRegFlat(RegIndex idx) override; 45913865Sgabeblack@google.com void setVecRegFlat(RegIndex idx, const VecRegContainer& val) override; 46012109SRekai.GonzalezAlberquilla@arm.com 46112109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem> 46213557Sgabeblack@google.com VecLaneT<VecElem, true> 46313865Sgabeblack@google.com readVecLaneFlat(RegIndex idx, int lId) const 46412109SRekai.GonzalezAlberquilla@arm.com { 46512109SRekai.GonzalezAlberquilla@arm.com return cpu->template readArchVecLane<VecElem>(idx, lId, 46612109SRekai.GonzalezAlberquilla@arm.com thread->threadId()); 46712109SRekai.GonzalezAlberquilla@arm.com } 46812109SRekai.GonzalezAlberquilla@arm.com 46912109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 47013865Sgabeblack@google.com void 47113865Sgabeblack@google.com setVecLaneFlat(int idx, int lId, const LD& val) 47212109SRekai.GonzalezAlberquilla@arm.com { 47312109SRekai.GonzalezAlberquilla@arm.com cpu->template setArchVecLane(idx, lId, thread->threadId(), val); 47412109SRekai.GonzalezAlberquilla@arm.com } 47512109SRekai.GonzalezAlberquilla@arm.com 47613865Sgabeblack@google.com const VecElem &readVecElemFlat(RegIndex idx, 47713865Sgabeblack@google.com const ElemIndex& elemIndex) const override; 47813865Sgabeblack@google.com void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx, 47913865Sgabeblack@google.com const VecElem& val) override; 48012109SRekai.GonzalezAlberquilla@arm.com 48113865Sgabeblack@google.com const VecPredRegContainer& readVecPredRegFlat(RegIndex idx) const override; 48213865Sgabeblack@google.com VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) override; 48313865Sgabeblack@google.com void setVecPredRegFlat(RegIndex idx, 48413865Sgabeblack@google.com const VecPredRegContainer& val) override; 48513610Sgiacomo.gabrielli@arm.com 48613865Sgabeblack@google.com RegVal readCCRegFlat(RegIndex idx) const override; 48713865Sgabeblack@google.com void setCCRegFlat(RegIndex idx, RegVal val) override; 4882817Sksewell@umich.edu}; 4892817Sksewell@umich.edu 4902817Sksewell@umich.edu#endif 491