History log of /gem5/src/arch/x86/registers.hh
Revision Date Author Comments
# 13622:ba31c2a23eca 21-Nov-2018 Gabe Black <gabeblack@google.com>

cpu, arch: Replace the CCReg type with RegVal.

Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.

Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>


# 13613:a19963be12ca 20-Nov-2018 Gabe Black <gabeblack@google.com>

x86: Stop using/defining some ISA specific register types.

These have been replaced with the generic RegVal type.

Change-Id: I75c1134212067dea43aa0903d813633e06f3d6c6
Reviewed-on: https://gem5-review.googlesource.com/c/14476
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>


# 13611:c8b7847b4171 19-Nov-2018 Gabe Black <gabeblack@google.com>

arch: cpu: Rename *FloatRegBits* to *FloatReg*.

Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.

Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>


# 13610:5d5404ac6288 16-Oct-2018 Giacomo Gabrielli <giacomo.gabrielli@arm.com>

arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>


# 13592:b8972ccebd63 19-Nov-2018 Gabe Black <gabeblack@google.com>

base: arch: Get rid of the now unused FloatRegVal type.

This type is no longer used since FP registers are accessed as integer
bit patterns.

Change-Id: I1070f9443d6247165fd64c6bc041811c28287e9f
Reviewed-on: https://gem5-review.googlesource.com/c/14459
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>


# 13556:9f57bb56153a 13-Oct-2018 Gabe Black <gabeblack@google.com>

arch: Make the ISA register types aliases for the global types.

The ISA specific types can thus be phased out.

Change-Id: I8ea531a099fad140a4ec9c91cd972fe044111d60
Reviewed-on: https://gem5-review.googlesource.com/c/13623
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>


# 13338:c59f7e47e31d 15-Oct-2018 Gabe Black <gabeblack@google.com>

arch: Get rid of the unused type AnyReg.

This type is defined for all the ISAs but isn't used by anything.

Change-Id: I659a0c5abc7883d82fedd1cac2cd103612d315c8
Reviewed-on: https://gem5-review.googlesource.com/c/13539
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>


# 12109:f29e9c5418aa 05-Apr-2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com>

cpu: Added interface for vector reg file

This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.

This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.

This requires implementing the vector register file for the different
models using the VecRegContainer class.

This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.

The changes also affect how the remote_gdb connection works.

There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.

Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.

Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705


# 12104:edd63f9c6184 05-Apr-2017 Nathanael Premillieu <nathanael.premillieu@arm.com>

arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700


# 11300:b3f2de9ff2bd 17-Jan-2016 Steve Reinhardt <steve.reinhardt@amd.com>

arch: get rid of unused LargestRead typedef


# 10935:acd48ddd725f 28-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

revert 5af8f40d8f2c


# 10934:5af8f40d8f2c 26-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

cpu: implements vector registers

This adds a vector register type. The type is defined as a std::array of a
fixed number of uint64_ts. The isa_parser.py has been modified to parse vector
register operands and generate the required code. Different cpus have vector
register files now.


# 9921:ee049bfce978 15-Oct-2013 Yasuko Eckert <yasuko.eckert@amd.com>

arch/x86: add support for explicit CC register file

Convert condition code registers from being specialized
("pseudo") integer registers to using the recently
added CC register class.

Nilay Vaish also contributed to this patch.


# 9920:028e4da64b42 15-Oct-2013 Yasuko Eckert <yasuko.eckert@amd.com>

cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.


# 9918:2c7219e2d999 15-Oct-2013 Steve Reinhardt <steve.reinhardt@amd.com>

cpu: rename *_DepTag constants to *_Reg_Base

Make these names more meaningful.

Specifically, made these substitutions:

s/FP_Base_DepTag/FP_Reg_Base/g;
s/Ctrl_Base_DepTag/Misc_Reg_Base/g;
s/Max_DepTag/Max_Reg_Index/g;


# 9917:7274310be1bb 15-Oct-2013 Steve Reinhardt <steve.reinhardt@amd.com>

isa: clean up register constants

Clean up and add some consistency to the *_Base_DepTag
constants as well as some related register constants:
- Get rid of NumMiscArchRegs, TotalArchRegs, and TotalDataRegs
since they're never used and not always defined
- Set FP_Base_DepTag = NumIntRegs when possible (i.e.,
every case except x86)
- Set Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs
(this was true before, but wasn't always expressed
that way)
- Drastically reduce the number of arbitrary constants
appearing in these calculations


# 9046:a1104cc13db2 05-Jun-2012 Ali Saidi <Ali.Saidi@ARM.com>

O3: Clean up the O3 structures and try to pack them a bit better.

DynInst is extremely large the hope is that this re-organization will put the
most used members close to each other.


# 8961:ff4762285f99 23-Apr-2012 Gabe Black <gblack@eecs.umich.edu>

ISA: Put parser generated files in a "generated" directory.

This is to avoid collision with non-generated files.


# 8229:78bf55f23338 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: sort all includes


# 7811:a8fc35183c10 03-Jan-2011 Steve Reinhardt <steve.reinhardt@amd.com>

Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.


# 7649:a6a6177a5ffa 25-Aug-2010 Min Kyu Jeong <minkyu.jeong@arm.com>

ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)

When decoding a srs instruction, invalid mode encoding returns invalid instruction.
This can happen when garbage instructions are fetched from mispredicted path


# 7629:0f0c231e3e97 23-Aug-2010 Gabe Black <gblack@eecs.umich.edu>

X86: Create a directory for files that define register indexes.

This is to help tidy up arch/x86. These files should not be used external to
the ISA.


# 7087:fb8d5786ff30 24-May-2010 Nathan Binkert <nate@binkert.org>

copyright: Change HP copyright on x86 code to be more friendly


# 6329:5d8b91875859 09-Jul-2009 Gabe Black <gblack@eecs.umich.edu>

Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.