registers.hh revision 6329:5d8b91875859
111420Sdavid.guillen@arm.com/* 211420Sdavid.guillen@arm.com * Copyright (c) 2007 The Hewlett-Packard Development Company 311420Sdavid.guillen@arm.com * All rights reserved. 411420Sdavid.guillen@arm.com * 511420Sdavid.guillen@arm.com * Redistribution and use of this software in source and binary forms, 611420Sdavid.guillen@arm.com * with or without modification, are permitted provided that the 711420Sdavid.guillen@arm.com * following conditions are met: 811420Sdavid.guillen@arm.com * 911420Sdavid.guillen@arm.com * The software must be used only for Non-Commercial Use which means any 1011420Sdavid.guillen@arm.com * use which is NOT directed to receiving any direct monetary 1111420Sdavid.guillen@arm.com * compensation for, or commercial advantage from such use. Illustrative 1211420Sdavid.guillen@arm.com * examples of non-commercial use are academic research, personal study, 1311420Sdavid.guillen@arm.com * teaching, education and corporate research & development. 1411420Sdavid.guillen@arm.com * Illustrative examples of commercial use are distributing products for 1511420Sdavid.guillen@arm.com * commercial advantage and providing services using the software for 1611420Sdavid.guillen@arm.com * commercial advantage. 1711420Sdavid.guillen@arm.com * 1811420Sdavid.guillen@arm.com * If you wish to use this software or functionality therein that may be 1911420Sdavid.guillen@arm.com * covered by patents for commercial use, please contact: 2011420Sdavid.guillen@arm.com * Director of Intellectual Property Licensing 2111420Sdavid.guillen@arm.com * Office of Strategy and Technology 2211420Sdavid.guillen@arm.com * Hewlett-Packard Company 2311420Sdavid.guillen@arm.com * 1501 Page Mill Road 2411420Sdavid.guillen@arm.com * Palo Alto, California 94304 2511420Sdavid.guillen@arm.com * 2611420Sdavid.guillen@arm.com * Redistributions of source code must retain the above copyright notice, 2711420Sdavid.guillen@arm.com * this list of conditions and the following disclaimer. Redistributions 2811420Sdavid.guillen@arm.com * in binary form must reproduce the above copyright notice, this list of 2911420Sdavid.guillen@arm.com * conditions and the following disclaimer in the documentation and/or 3011420Sdavid.guillen@arm.com * other materials provided with the distribution. Neither the name of 3111420Sdavid.guillen@arm.com * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 3211420Sdavid.guillen@arm.com * contributors may be used to endorse or promote products derived from 3311420Sdavid.guillen@arm.com * this software without specific prior written permission. No right of 3411420Sdavid.guillen@arm.com * sublicense is granted herewith. Derivatives of the software and 3511420Sdavid.guillen@arm.com * output created using the software may be prepared, but only for 3611420Sdavid.guillen@arm.com * Non-Commercial Uses. Derivatives of the software may be shared with 3711420Sdavid.guillen@arm.com * others provided: (i) the others agree to abide by the list of 3811988Sandreas.sandberg@arm.com * conditions herein which includes the Non-Commercial Use restrictions; 3911420Sdavid.guillen@arm.com * and (ii) such Derivatives of the software include the above copyright 4011420Sdavid.guillen@arm.com * notice to acknowledge the contribution from this software where 4111420Sdavid.guillen@arm.com * applicable, this list of conditions and the disclaimer below. 4211420Sdavid.guillen@arm.com * 4311420Sdavid.guillen@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 4411420Sdavid.guillen@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 4511420Sdavid.guillen@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 4611988Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 4711988Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 4811988Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 4911420Sdavid.guillen@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 5011420Sdavid.guillen@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 5111420Sdavid.guillen@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_REGISTERS_HH__ 59#define __ARCH_X86_REGISTERS_HH__ 60 61#include "arch/x86/intregs.hh" 62#include "arch/x86/max_inst_regs.hh" 63#include "arch/x86/miscregs.hh" 64#include "arch/x86/x86_traits.hh" 65 66namespace X86ISA 67{ 68using X86ISAInst::MaxInstSrcRegs; 69using X86ISAInst::MaxInstDestRegs; 70const int NumMiscArchRegs = NUM_MISCREGS; 71const int NumMiscRegs = NUM_MISCREGS; 72 73const int NumIntArchRegs = NUM_INTREGS; 74const int NumIntRegs = 75 NumIntArchRegs + NumMicroIntRegs + 76 NumPseudoIntRegs + NumImplicitIntRegs; 77 78//Each 128 bit xmm register is broken into two effective 64 bit registers. 79const int NumFloatRegs = 80 NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs; 81const int NumFloatArchRegs = NumFloatRegs + 8; 82 83// These enumerate all the registers for dependence tracking. 84enum DependenceTags { 85 //There are 16 microcode registers at the moment. This is an 86 //unusually large constant to make sure there isn't overflow. 87 FP_Base_DepTag = 128, 88 Ctrl_Base_DepTag = 89 FP_Base_DepTag + 90 //mmx/x87 registers 91 8 + 92 //xmm registers 93 16 * 2 + 94 //The microcode fp registers 95 8 + 96 //The indices that are mapped over the fp stack 97 8 98}; 99 100// semantically meaningful register indices 101//There is no such register in X86 102const int ZeroReg = NUM_INTREGS; 103const int StackPointerReg = INTREG_RSP; 104//X86 doesn't seem to have a link register 105const int ReturnAddressReg = 0; 106const int ReturnValueReg = INTREG_RAX; 107const int FramePointerReg = INTREG_RBP; 108 109// Some OS syscalls use a second register (rdx) to return a second 110// value 111const int SyscallPseudoReturnReg = INTREG_RDX; 112 113typedef uint64_t IntReg; 114//XXX Should this be a 128 bit structure for XMM memory ops? 115typedef uint64_t LargestRead; 116typedef uint64_t MiscReg; 117 118//These floating point types are correct for mmx, but not 119//technically for x87 (80 bits) or at all for xmm (128 bits) 120typedef double FloatReg; 121typedef uint64_t FloatRegBits; 122typedef union 123{ 124 IntReg intReg; 125 FloatReg fpReg; 126 MiscReg ctrlReg; 127} AnyReg; 128 129typedef uint16_t RegIndex; 130 131}; // namespace X86ISA 132 133#endif // __ARCH_X86_REGFILE_HH__ 134