12330SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152330SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162330SN/A * All rights reserved. 172330SN/A * 182330SN/A * Redistribution and use in source and binary forms, with or without 192330SN/A * modification, are permitted provided that the following conditions are 202330SN/A * met: redistributions of source code must retain the above copyright 212330SN/A * notice, this list of conditions and the following disclaimer; 222330SN/A * redistributions in binary form must reproduce the above copyright 232330SN/A * notice, this list of conditions and the following disclaimer in the 242330SN/A * documentation and/or other materials provided with the distribution; 252330SN/A * neither the name of the copyright holders nor the names of its 262330SN/A * contributors may be used to endorse or promote products derived from 272330SN/A * this software without specific prior written permission. 282330SN/A * 292330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422330SN/A */ 432330SN/A 442683Sktlim@umich.edu#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 452683Sktlim@umich.edu#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 462315SN/A 472972Sgblack@eecs.umich.edu#include "arch/types.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 492315SN/A#include "cpu/checker/cpu.hh" 502683Sktlim@umich.edu#include "cpu/simple_thread.hh" 512680SN/A#include "cpu/thread_context.hh" 528733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 532315SN/A 542315SN/Aclass EndQuiesceEvent; 5513905Sgabeblack@google.comnamespace Kernel { 5613905Sgabeblack@google.com class Statistics; 5713905Sgabeblack@google.com}; 583548Sgblack@eecs.umich.edunamespace TheISA { 599020Sgblack@eecs.umich.edu class Decoder; 602330SN/A}; 612315SN/A 622350SN/A/** 632680SN/A * Derived ThreadContext class for use with the Checker. The template 642680SN/A * parameter is the ThreadContext class used by the specific CPU being 652683Sktlim@umich.edu * verified. This CheckerThreadContext is then used by the main CPU 662683Sktlim@umich.edu * in place of its usual ThreadContext class. It handles updating the 672683Sktlim@umich.edu * checker's state any time state is updated externally through the 682683Sktlim@umich.edu * ThreadContext. 692350SN/A */ 702680SN/Atemplate <class TC> 712680SN/Aclass CheckerThreadContext : public ThreadContext 722315SN/A{ 732315SN/A public: 742680SN/A CheckerThreadContext(TC *actual_tc, 752683Sktlim@umich.edu CheckerCPU *checker_cpu) 762683Sktlim@umich.edu : actualTC(actual_tc), checkerTC(checker_cpu->thread), 772330SN/A checkerCPU(checker_cpu) 782315SN/A { } 792315SN/A 802315SN/A private: 812683Sktlim@umich.edu /** The main CPU's ThreadContext, or class that implements the 822683Sktlim@umich.edu * ThreadContext interface. */ 832680SN/A TC *actualTC; 842683Sktlim@umich.edu /** The checker's own SimpleThread. Will be updated any time 852683Sktlim@umich.edu * anything uses this ThreadContext to externally update a 862683Sktlim@umich.edu * thread's state. */ 872683Sktlim@umich.edu SimpleThread *checkerTC; 882683Sktlim@umich.edu /** Pointer to the checker CPU. */ 892315SN/A CheckerCPU *checkerCPU; 902315SN/A 912315SN/A public: 922315SN/A 9313628SAndrea.Mondelli@ucf.edu BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); } 942315SN/A 9513628SAndrea.Mondelli@ucf.edu uint32_t socketId() const override { return actualTC->socketId(); } 9610190Sakash.bagdia@arm.com 9713628SAndrea.Mondelli@ucf.edu int cpuId() const override { return actualTC->cpuId(); } 988733Sgeoffrey.blake@arm.com 9913628SAndrea.Mondelli@ucf.edu ContextID contextId() const override { return actualTC->contextId(); } 1008733Sgeoffrey.blake@arm.com 10113865Sgabeblack@google.com void 10213865Sgabeblack@google.com setContextId(ContextID id) override 1032315SN/A { 1048733Sgeoffrey.blake@arm.com actualTC->setContextId(id); 1058733Sgeoffrey.blake@arm.com checkerTC->setContextId(id); 1062315SN/A } 1072315SN/A 1088733Sgeoffrey.blake@arm.com /** Returns this thread's ID number. */ 10913628SAndrea.Mondelli@ucf.edu int threadId() const override { return actualTC->threadId(); } 11013865Sgabeblack@google.com void 11113865Sgabeblack@google.com setThreadId(int id) override 1128733Sgeoffrey.blake@arm.com { 1138733Sgeoffrey.blake@arm.com checkerTC->setThreadId(id); 1148733Sgeoffrey.blake@arm.com actualTC->setThreadId(id); 1158733Sgeoffrey.blake@arm.com } 1162315SN/A 11713628SAndrea.Mondelli@ucf.edu BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); } 1184997Sgblack@eecs.umich.edu 11913628SAndrea.Mondelli@ucf.edu BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); } 1204997Sgblack@eecs.umich.edu 12113865Sgabeblack@google.com CheckerCPU * 12213865Sgabeblack@google.com getCheckerCpuPtr() override 1238887Sgeoffrey.blake@arm.com { 1248887Sgeoffrey.blake@arm.com return checkerCPU; 1258887Sgeoffrey.blake@arm.com } 1268733Sgeoffrey.blake@arm.com 12713693Sgiacomo.gabrielli@arm.com TheISA::ISA *getIsaPtr() override { return actualTC->getIsaPtr(); } 12813693Sgiacomo.gabrielli@arm.com 12913865Sgabeblack@google.com TheISA::Decoder * 13013865Sgabeblack@google.com getDecoderPtr() override 13113865Sgabeblack@google.com { 13213628SAndrea.Mondelli@ucf.edu return actualTC->getDecoderPtr(); 13313628SAndrea.Mondelli@ucf.edu } 1348733Sgeoffrey.blake@arm.com 13513628SAndrea.Mondelli@ucf.edu System *getSystemPtr() override { return actualTC->getSystemPtr(); } 1362315SN/A 13713905Sgabeblack@google.com ::Kernel::Statistics * 13813865Sgabeblack@google.com getKernelStats() override 13913865Sgabeblack@google.com { 14013865Sgabeblack@google.com return actualTC->getKernelStats(); 14113865Sgabeblack@google.com } 1422690Sktlim@umich.edu 14313628SAndrea.Mondelli@ucf.edu Process *getProcessPtr() override { return actualTC->getProcessPtr(); } 1447679Sgblack@eecs.umich.edu 14513628SAndrea.Mondelli@ucf.edu void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); } 14611886Sbrandon.potter@amd.com 14713628SAndrea.Mondelli@ucf.edu PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); } 1482690Sktlim@umich.edu 14914022Sgabeblack@google.com PortProxy & 15013865Sgabeblack@google.com getVirtProxy() override 15113865Sgabeblack@google.com { 15213865Sgabeblack@google.com return actualTC->getVirtProxy(); 15313865Sgabeblack@google.com } 1548733Sgeoffrey.blake@arm.com 15513865Sgabeblack@google.com void 15613865Sgabeblack@google.com initMemProxies(ThreadContext *tc) override 15713865Sgabeblack@google.com { 15813865Sgabeblack@google.com actualTC->initMemProxies(tc); 15913865Sgabeblack@google.com } 1608733Sgeoffrey.blake@arm.com 16113865Sgabeblack@google.com void 16213865Sgabeblack@google.com connectMemPorts(ThreadContext *tc) 1638733Sgeoffrey.blake@arm.com { 1648733Sgeoffrey.blake@arm.com actualTC->connectMemPorts(tc); 1658733Sgeoffrey.blake@arm.com } 1668809Sgblack@eecs.umich.edu 1678733Sgeoffrey.blake@arm.com /** Executes a syscall in SE mode. */ 16813865Sgabeblack@google.com void 16913865Sgabeblack@google.com syscall(int64_t callnum, Fault *fault) override 17013865Sgabeblack@google.com { 17113865Sgabeblack@google.com return actualTC->syscall(callnum, fault); 17213865Sgabeblack@google.com } 1732315SN/A 17413628SAndrea.Mondelli@ucf.edu Status status() const override { return actualTC->status(); } 1752315SN/A 17613865Sgabeblack@google.com void 17713865Sgabeblack@google.com setStatus(Status new_status) override 1782330SN/A { 1792680SN/A actualTC->setStatus(new_status); 1802680SN/A checkerTC->setStatus(new_status); 1812330SN/A } 1822315SN/A 18310407Smitch.hayenga@arm.com /// Set the status to Active. 18413628SAndrea.Mondelli@ucf.edu void activate() override { actualTC->activate(); } 1852315SN/A 1862315SN/A /// Set the status to Suspended. 18713865Sgabeblack@google.com void suspend() override { actualTC->suspend(); } 1882315SN/A 1892315SN/A /// Set the status to Halted. 19013865Sgabeblack@google.com void halt() override { actualTC->halt(); } 1912315SN/A 19213865Sgabeblack@google.com void dumpFuncProfile() override { actualTC->dumpFuncProfile(); } 1932315SN/A 19413865Sgabeblack@google.com void 19513865Sgabeblack@google.com takeOverFrom(ThreadContext *oldContext) override 1962315SN/A { 1972680SN/A actualTC->takeOverFrom(oldContext); 1983225Sktlim@umich.edu checkerTC->copyState(oldContext); 1992315SN/A } 2002315SN/A 20113865Sgabeblack@google.com void 20213865Sgabeblack@google.com regStats(const std::string &name) override 2038733Sgeoffrey.blake@arm.com { 2048733Sgeoffrey.blake@arm.com actualTC->regStats(name); 2058733Sgeoffrey.blake@arm.com checkerTC->regStats(name); 2068733Sgeoffrey.blake@arm.com } 2072315SN/A 20813865Sgabeblack@google.com EndQuiesceEvent * 20913865Sgabeblack@google.com getQuiesceEvent() override 21013865Sgabeblack@google.com { 21113628SAndrea.Mondelli@ucf.edu return actualTC->getQuiesceEvent(); 21213628SAndrea.Mondelli@ucf.edu } 2132315SN/A 21413865Sgabeblack@google.com Tick readLastActivate() override { return actualTC->readLastActivate(); } 21513865Sgabeblack@google.com Tick readLastSuspend() override { return actualTC->readLastSuspend(); } 2162315SN/A 21713865Sgabeblack@google.com void profileClear() override { return actualTC->profileClear(); } 21813865Sgabeblack@google.com void profileSample() override { return actualTC->profileSample(); } 2192315SN/A 2202315SN/A // @todo: Do I need this? 22113865Sgabeblack@google.com void 22213865Sgabeblack@google.com copyArchRegs(ThreadContext *tc) override 2232315SN/A { 2242680SN/A actualTC->copyArchRegs(tc); 2252680SN/A checkerTC->copyArchRegs(tc); 2262315SN/A } 2272315SN/A 22813865Sgabeblack@google.com void 22913865Sgabeblack@google.com clearArchRegs() override 2302315SN/A { 2312680SN/A actualTC->clearArchRegs(); 2322680SN/A checkerTC->clearArchRegs(); 2332315SN/A } 2342315SN/A 2352315SN/A // 2362315SN/A // New accessors for new decoder. 2372315SN/A // 23813865Sgabeblack@google.com RegVal 23913865Sgabeblack@google.com readIntReg(RegIndex reg_idx) const override 24013865Sgabeblack@google.com { 24113628SAndrea.Mondelli@ucf.edu return actualTC->readIntReg(reg_idx); 24213628SAndrea.Mondelli@ucf.edu } 2432315SN/A 24413557Sgabeblack@google.com RegVal 24513865Sgabeblack@google.com readFloatReg(RegIndex reg_idx) const override 24613557Sgabeblack@google.com { 24713611Sgabeblack@google.com return actualTC->readFloatReg(reg_idx); 24813557Sgabeblack@google.com } 2492315SN/A 25013865Sgabeblack@google.com const VecRegContainer & 25113865Sgabeblack@google.com readVecReg (const RegId ®) const override 25213865Sgabeblack@google.com { 25313865Sgabeblack@google.com return actualTC->readVecReg(reg); 25413865Sgabeblack@google.com } 25512109SRekai.GonzalezAlberquilla@arm.com 25612109SRekai.GonzalezAlberquilla@arm.com /** 25712109SRekai.GonzalezAlberquilla@arm.com * Read vector register for modification, hierarchical indexing. 25812109SRekai.GonzalezAlberquilla@arm.com */ 25913865Sgabeblack@google.com VecRegContainer & 26013865Sgabeblack@google.com getWritableVecReg (const RegId ®) override 26113865Sgabeblack@google.com { 26213865Sgabeblack@google.com return actualTC->getWritableVecReg(reg); 26313865Sgabeblack@google.com } 26412109SRekai.GonzalezAlberquilla@arm.com 26512109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 26612109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 26712109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 26812109SRekai.GonzalezAlberquilla@arm.com ConstVecLane8 26913865Sgabeblack@google.com readVec8BitLaneReg(const RegId ®) const override 27013865Sgabeblack@google.com { 27113865Sgabeblack@google.com return actualTC->readVec8BitLaneReg(reg); 27213865Sgabeblack@google.com } 27312109SRekai.GonzalezAlberquilla@arm.com 27412109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 27512109SRekai.GonzalezAlberquilla@arm.com ConstVecLane16 27613865Sgabeblack@google.com readVec16BitLaneReg(const RegId ®) const override 27713865Sgabeblack@google.com { 27813865Sgabeblack@google.com return actualTC->readVec16BitLaneReg(reg); 27913865Sgabeblack@google.com } 28012109SRekai.GonzalezAlberquilla@arm.com 28112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 28212109SRekai.GonzalezAlberquilla@arm.com ConstVecLane32 28313865Sgabeblack@google.com readVec32BitLaneReg(const RegId ®) const override 28413865Sgabeblack@google.com { 28513865Sgabeblack@google.com return actualTC->readVec32BitLaneReg(reg); 28613865Sgabeblack@google.com } 28712109SRekai.GonzalezAlberquilla@arm.com 28812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 28912109SRekai.GonzalezAlberquilla@arm.com ConstVecLane64 29013865Sgabeblack@google.com readVec64BitLaneReg(const RegId ®) const override 29113865Sgabeblack@google.com { 29213865Sgabeblack@google.com return actualTC->readVec64BitLaneReg(reg); 29313865Sgabeblack@google.com } 29412109SRekai.GonzalezAlberquilla@arm.com 29512109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 29613865Sgabeblack@google.com virtual void 29713865Sgabeblack@google.com setVecLane(const RegId ®, 29813865Sgabeblack@google.com const LaneData<LaneSize::Byte> &val) override 29913865Sgabeblack@google.com { 30013865Sgabeblack@google.com return actualTC->setVecLane(reg, val); 30113865Sgabeblack@google.com } 30213865Sgabeblack@google.com virtual void 30313865Sgabeblack@google.com setVecLane(const RegId ®, 30413865Sgabeblack@google.com const LaneData<LaneSize::TwoByte> &val) override 30513865Sgabeblack@google.com { 30613865Sgabeblack@google.com return actualTC->setVecLane(reg, val); 30713865Sgabeblack@google.com } 30813865Sgabeblack@google.com virtual void 30913865Sgabeblack@google.com setVecLane(const RegId ®, 31013865Sgabeblack@google.com const LaneData<LaneSize::FourByte> &val) override 31113865Sgabeblack@google.com { 31213865Sgabeblack@google.com return actualTC->setVecLane(reg, val); 31313865Sgabeblack@google.com } 31413865Sgabeblack@google.com virtual void 31513865Sgabeblack@google.com setVecLane(const RegId ®, 31613865Sgabeblack@google.com const LaneData<LaneSize::EightByte> &val) override 31713865Sgabeblack@google.com { 31813865Sgabeblack@google.com return actualTC->setVecLane(reg, val); 31913865Sgabeblack@google.com } 32012109SRekai.GonzalezAlberquilla@arm.com /** @} */ 32112109SRekai.GonzalezAlberquilla@arm.com 32213865Sgabeblack@google.com const VecElem & 32313865Sgabeblack@google.com readVecElem(const RegId& reg) const override 32413865Sgabeblack@google.com { 32513865Sgabeblack@google.com return actualTC->readVecElem(reg); 32613865Sgabeblack@google.com } 32712109SRekai.GonzalezAlberquilla@arm.com 32813865Sgabeblack@google.com const VecPredRegContainer & 32913865Sgabeblack@google.com readVecPredReg(const RegId& reg) const override 33013865Sgabeblack@google.com { 33113865Sgabeblack@google.com return actualTC->readVecPredReg(reg); 33213865Sgabeblack@google.com } 33313610Sgiacomo.gabrielli@arm.com 33413865Sgabeblack@google.com VecPredRegContainer & 33513865Sgabeblack@google.com getWritableVecPredReg(const RegId& reg) override 33613865Sgabeblack@google.com { 33713865Sgabeblack@google.com return actualTC->getWritableVecPredReg(reg); 33813865Sgabeblack@google.com } 33913610Sgiacomo.gabrielli@arm.com 34013865Sgabeblack@google.com RegVal 34113865Sgabeblack@google.com readCCReg(RegIndex reg_idx) const override 34213865Sgabeblack@google.com { 34313865Sgabeblack@google.com return actualTC->readCCReg(reg_idx); 34413865Sgabeblack@google.com } 3459920Syasuko.eckert@amd.com 34613557Sgabeblack@google.com void 34713865Sgabeblack@google.com setIntReg(RegIndex reg_idx, RegVal val) override 3482315SN/A { 3492680SN/A actualTC->setIntReg(reg_idx, val); 3502680SN/A checkerTC->setIntReg(reg_idx, val); 3512315SN/A } 3522315SN/A 35313557Sgabeblack@google.com void 35413865Sgabeblack@google.com setFloatReg(RegIndex reg_idx, RegVal val) override 3552669SN/A { 35613611Sgabeblack@google.com actualTC->setFloatReg(reg_idx, val); 35713611Sgabeblack@google.com checkerTC->setFloatReg(reg_idx, val); 3582315SN/A } 3592315SN/A 36013557Sgabeblack@google.com void 36113628SAndrea.Mondelli@ucf.edu setVecReg(const RegId& reg, const VecRegContainer& val) override 36212109SRekai.GonzalezAlberquilla@arm.com { 36312109SRekai.GonzalezAlberquilla@arm.com actualTC->setVecReg(reg, val); 36412109SRekai.GonzalezAlberquilla@arm.com checkerTC->setVecReg(reg, val); 36512109SRekai.GonzalezAlberquilla@arm.com } 36612109SRekai.GonzalezAlberquilla@arm.com 36713557Sgabeblack@google.com void 36813628SAndrea.Mondelli@ucf.edu setVecElem(const RegId& reg, const VecElem& val) override 36912109SRekai.GonzalezAlberquilla@arm.com { 37012109SRekai.GonzalezAlberquilla@arm.com actualTC->setVecElem(reg, val); 37112109SRekai.GonzalezAlberquilla@arm.com checkerTC->setVecElem(reg, val); 37212109SRekai.GonzalezAlberquilla@arm.com } 37312109SRekai.GonzalezAlberquilla@arm.com 37413557Sgabeblack@google.com void 37513628SAndrea.Mondelli@ucf.edu setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override 37613610Sgiacomo.gabrielli@arm.com { 37713610Sgiacomo.gabrielli@arm.com actualTC->setVecPredReg(reg, val); 37813610Sgiacomo.gabrielli@arm.com checkerTC->setVecPredReg(reg, val); 37913610Sgiacomo.gabrielli@arm.com } 38013610Sgiacomo.gabrielli@arm.com 38113610Sgiacomo.gabrielli@arm.com void 38213865Sgabeblack@google.com setCCReg(RegIndex reg_idx, RegVal val) override 3839920Syasuko.eckert@amd.com { 3849920Syasuko.eckert@amd.com actualTC->setCCReg(reg_idx, val); 3859920Syasuko.eckert@amd.com checkerTC->setCCReg(reg_idx, val); 3869920Syasuko.eckert@amd.com } 3879920Syasuko.eckert@amd.com 3888733Sgeoffrey.blake@arm.com /** Reads this thread's PC state. */ 38913865Sgabeblack@google.com TheISA::PCState pcState() const override { return actualTC->pcState(); } 3902315SN/A 3918733Sgeoffrey.blake@arm.com /** Sets this thread's PC state. */ 39213557Sgabeblack@google.com void 39313628SAndrea.Mondelli@ucf.edu pcState(const TheISA::PCState &val) override 3942315SN/A { 3958733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 3968733Sgeoffrey.blake@arm.com val, checkerTC->pcState()); 3978733Sgeoffrey.blake@arm.com checkerTC->pcState(val); 3982315SN/A checkerCPU->recordPCChange(val); 3998733Sgeoffrey.blake@arm.com return actualTC->pcState(val); 4002315SN/A } 4012315SN/A 40213557Sgabeblack@google.com void 40313557Sgabeblack@google.com setNPC(Addr val) 40411886Sbrandon.potter@amd.com { 40511886Sbrandon.potter@amd.com checkerTC->setNPC(val); 40611886Sbrandon.potter@amd.com actualTC->setNPC(val); 40711886Sbrandon.potter@amd.com } 40811886Sbrandon.potter@amd.com 40913557Sgabeblack@google.com void 41013628SAndrea.Mondelli@ucf.edu pcStateNoRecord(const TheISA::PCState &val) override 4112315SN/A { 4128733Sgeoffrey.blake@arm.com return actualTC->pcState(val); 4132315SN/A } 4142315SN/A 4158733Sgeoffrey.blake@arm.com /** Reads this thread's PC. */ 41613865Sgabeblack@google.com Addr instAddr() const override { return actualTC->instAddr(); } 4172669SN/A 4188733Sgeoffrey.blake@arm.com /** Reads this thread's next PC. */ 41913865Sgabeblack@google.com Addr nextInstAddr() const override { return actualTC->nextInstAddr(); } 4208733Sgeoffrey.blake@arm.com 4218733Sgeoffrey.blake@arm.com /** Reads this thread's next PC. */ 42213865Sgabeblack@google.com MicroPC microPC() const override { return actualTC->microPC(); } 4232669SN/A 42413865Sgabeblack@google.com RegVal 42513865Sgabeblack@google.com readMiscRegNoEffect(RegIndex misc_reg) const override 42613865Sgabeblack@google.com { 42713865Sgabeblack@google.com return actualTC->readMiscRegNoEffect(misc_reg); 42813865Sgabeblack@google.com } 4294172Ssaidi@eecs.umich.edu 43013865Sgabeblack@google.com RegVal 43113865Sgabeblack@google.com readMiscReg(RegIndex misc_reg) override 43213865Sgabeblack@google.com { 43313865Sgabeblack@google.com return actualTC->readMiscReg(misc_reg); 43413865Sgabeblack@google.com } 4352315SN/A 43613557Sgabeblack@google.com void 43713865Sgabeblack@google.com setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override 4384172Ssaidi@eecs.umich.edu { 4398733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 4408733Sgeoffrey.blake@arm.com " and O3..\n", misc_reg); 4414172Ssaidi@eecs.umich.edu checkerTC->setMiscRegNoEffect(misc_reg, val); 4424172Ssaidi@eecs.umich.edu actualTC->setMiscRegNoEffect(misc_reg, val); 4434172Ssaidi@eecs.umich.edu } 4442315SN/A 44513557Sgabeblack@google.com void 44613865Sgabeblack@google.com setMiscReg(RegIndex misc_reg, RegVal val) override 4472315SN/A { 4488733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 4498733Sgeoffrey.blake@arm.com " and O3..\n", misc_reg); 4502680SN/A checkerTC->setMiscReg(misc_reg, val); 4513468Sgblack@eecs.umich.edu actualTC->setMiscReg(misc_reg, val); 4522315SN/A } 4532315SN/A 45413557Sgabeblack@google.com RegId 45513628SAndrea.Mondelli@ucf.edu flattenRegId(const RegId& regId) const override 45613557Sgabeblack@google.com { 45712106SRekai.GonzalezAlberquilla@arm.com return actualTC->flattenRegId(regId); 45812106SRekai.GonzalezAlberquilla@arm.com } 4598733Sgeoffrey.blake@arm.com 46013865Sgabeblack@google.com unsigned 46113865Sgabeblack@google.com readStCondFailures() const override 46213865Sgabeblack@google.com { 46313865Sgabeblack@google.com return actualTC->readStCondFailures(); 46413865Sgabeblack@google.com } 4652315SN/A 46613557Sgabeblack@google.com void 46713628SAndrea.Mondelli@ucf.edu setStCondFailures(unsigned sc_failures) override 4682315SN/A { 4692680SN/A actualTC->setStCondFailures(sc_failures); 4702315SN/A } 4712315SN/A 47213865Sgabeblack@google.com Counter 47313865Sgabeblack@google.com readFuncExeInst() const override 47413865Sgabeblack@google.com { 47513865Sgabeblack@google.com return actualTC->readFuncExeInst(); 47613865Sgabeblack@google.com } 4779426SAndreas.Sandberg@ARM.com 47813865Sgabeblack@google.com RegVal 47913865Sgabeblack@google.com readIntRegFlat(RegIndex idx) const override 48013865Sgabeblack@google.com { 48113628SAndrea.Mondelli@ucf.edu return actualTC->readIntRegFlat(idx); 48213628SAndrea.Mondelli@ucf.edu } 4839426SAndreas.Sandberg@ARM.com 48413557Sgabeblack@google.com void 48513865Sgabeblack@google.com setIntRegFlat(RegIndex idx, RegVal val) override 48613557Sgabeblack@google.com { 48713557Sgabeblack@google.com actualTC->setIntRegFlat(idx, val); 48813557Sgabeblack@google.com } 4899426SAndreas.Sandberg@ARM.com 49013557Sgabeblack@google.com RegVal 49113865Sgabeblack@google.com readFloatRegFlat(RegIndex idx) const override 49213557Sgabeblack@google.com { 49313611Sgabeblack@google.com return actualTC->readFloatRegFlat(idx); 49413557Sgabeblack@google.com } 4959426SAndreas.Sandberg@ARM.com 49613557Sgabeblack@google.com void 49713865Sgabeblack@google.com setFloatRegFlat(RegIndex idx, RegVal val) override 49813557Sgabeblack@google.com { 49913611Sgabeblack@google.com actualTC->setFloatRegFlat(idx, val); 50013557Sgabeblack@google.com } 5019920Syasuko.eckert@amd.com 50213557Sgabeblack@google.com const VecRegContainer & 50313865Sgabeblack@google.com readVecRegFlat(RegIndex idx) const override 50413557Sgabeblack@google.com { 50513557Sgabeblack@google.com return actualTC->readVecRegFlat(idx); 50613557Sgabeblack@google.com } 50712109SRekai.GonzalezAlberquilla@arm.com 50812109SRekai.GonzalezAlberquilla@arm.com /** 50912109SRekai.GonzalezAlberquilla@arm.com * Read vector register for modification, flat indexing. 51012109SRekai.GonzalezAlberquilla@arm.com */ 51113557Sgabeblack@google.com VecRegContainer & 51213865Sgabeblack@google.com getWritableVecRegFlat(RegIndex idx) override 51313557Sgabeblack@google.com { 51413557Sgabeblack@google.com return actualTC->getWritableVecRegFlat(idx); 51513557Sgabeblack@google.com } 51612109SRekai.GonzalezAlberquilla@arm.com 51713865Sgabeblack@google.com void 51813865Sgabeblack@google.com setVecRegFlat(RegIndex idx, const VecRegContainer& val) override 51913865Sgabeblack@google.com { 52013865Sgabeblack@google.com actualTC->setVecRegFlat(idx, val); 52113865Sgabeblack@google.com } 52212109SRekai.GonzalezAlberquilla@arm.com 52313865Sgabeblack@google.com const VecElem & 52413865Sgabeblack@google.com readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override 52513865Sgabeblack@google.com { 52613865Sgabeblack@google.com return actualTC->readVecElemFlat(idx, elem_idx); 52713865Sgabeblack@google.com } 52812109SRekai.GonzalezAlberquilla@arm.com 52913865Sgabeblack@google.com void 53013865Sgabeblack@google.com setVecElemFlat(RegIndex idx, 53113865Sgabeblack@google.com const ElemIndex& elem_idx, const VecElem& val) override 53213865Sgabeblack@google.com { 53313865Sgabeblack@google.com actualTC->setVecElemFlat(idx, elem_idx, val); 53413865Sgabeblack@google.com } 53512109SRekai.GonzalezAlberquilla@arm.com 53613865Sgabeblack@google.com const VecPredRegContainer & 53713865Sgabeblack@google.com readVecPredRegFlat(RegIndex idx) const override 53813865Sgabeblack@google.com { 53913865Sgabeblack@google.com return actualTC->readVecPredRegFlat(idx); 54013865Sgabeblack@google.com } 54113610Sgiacomo.gabrielli@arm.com 54213865Sgabeblack@google.com VecPredRegContainer & 54313865Sgabeblack@google.com getWritableVecPredRegFlat(RegIndex idx) override 54413865Sgabeblack@google.com { 54513865Sgabeblack@google.com return actualTC->getWritableVecPredRegFlat(idx); 54613865Sgabeblack@google.com } 54713610Sgiacomo.gabrielli@arm.com 54813865Sgabeblack@google.com void 54913865Sgabeblack@google.com setVecPredRegFlat(RegIndex idx, const VecPredRegContainer& val) override 55013865Sgabeblack@google.com { 55113865Sgabeblack@google.com actualTC->setVecPredRegFlat(idx, val); 55213865Sgabeblack@google.com } 55313610Sgiacomo.gabrielli@arm.com 55413865Sgabeblack@google.com RegVal 55513865Sgabeblack@google.com readCCRegFlat(RegIndex idx) const override 55613865Sgabeblack@google.com { 55713865Sgabeblack@google.com return actualTC->readCCRegFlat(idx); 55813865Sgabeblack@google.com } 5599920Syasuko.eckert@amd.com 56013865Sgabeblack@google.com void 56113865Sgabeblack@google.com setCCRegFlat(RegIndex idx, RegVal val) override 56213865Sgabeblack@google.com { 56313865Sgabeblack@google.com actualTC->setCCRegFlat(idx, val); 56413865Sgabeblack@google.com } 5652315SN/A}; 5662315SN/A 5672315SN/A#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 568