14120SN/A/*
24120SN/A * Copyright (c) 2007 The Hewlett-Packard Development Company
39917Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc.
44120SN/A * All rights reserved.
54120SN/A *
67087Snate@binkert.org * The license below extends only to copyright in the software and shall
77087Snate@binkert.org * not be construed as granting a license to any other intellectual
87087Snate@binkert.org * property including but not limited to intellectual property relating
97087Snate@binkert.org * to a hardware implementation of the functionality of the software
107087Snate@binkert.org * licensed hereunder.  You may use the software subject to the license
117087Snate@binkert.org * terms below provided that you ensure that this notice is replicated
127087Snate@binkert.org * unmodified and in its entirety in all distributions of the software,
137087Snate@binkert.org * modified or unmodified, in source code or in binary form.
144120SN/A *
157087Snate@binkert.org * Redistribution and use in source and binary forms, with or without
167087Snate@binkert.org * modification, are permitted provided that the following conditions are
177087Snate@binkert.org * met: redistributions of source code must retain the above copyright
187087Snate@binkert.org * notice, this list of conditions and the following disclaimer;
197087Snate@binkert.org * redistributions in binary form must reproduce the above copyright
207087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the
217087Snate@binkert.org * documentation and/or other materials provided with the distribution;
227087Snate@binkert.org * neither the name of the copyright holders nor the names of its
234120SN/A * contributors may be used to endorse or promote products derived from
247087Snate@binkert.org * this software without specific prior written permission.
254120SN/A *
264120SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
274120SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
284120SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
294120SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
304120SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
314120SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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344120SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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364120SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
374120SN/A *
384120SN/A * Authors: Gabe Black
394120SN/A */
404120SN/A
416329Sgblack@eecs.umich.edu#ifndef __ARCH_X86_REGISTERS_HH__
426329Sgblack@eecs.umich.edu#define __ARCH_X86_REGISTERS_HH__
436216SN/A
4413610Sgiacomo.gabrielli@arm.com#include "arch/generic/vec_pred_reg.hh"
4512109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/vec_reg.hh"
468961Sgblack@eecs.umich.edu#include "arch/x86/generated/max_inst_regs.hh"
477629Sgblack@eecs.umich.edu#include "arch/x86/regs/int.hh"
489921Syasuko.eckert@amd.com#include "arch/x86/regs/ccr.hh"
497629Sgblack@eecs.umich.edu#include "arch/x86/regs/misc.hh"
506315SN/A#include "arch/x86/x86_traits.hh"
514137SN/A
524120SN/Anamespace X86ISA
534120SN/A{
546329Sgblack@eecs.umich.eduusing X86ISAInst::MaxInstSrcRegs;
556329Sgblack@eecs.umich.eduusing X86ISAInst::MaxInstDestRegs;
569046SAli.Saidi@ARM.comusing X86ISAInst::MaxMiscDestRegs;
576329Sgblack@eecs.umich.educonst int NumMiscRegs = NUM_MISCREGS;
586313SN/A
596329Sgblack@eecs.umich.educonst int NumIntArchRegs = NUM_INTREGS;
609921Syasuko.eckert@amd.comconst int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
619921Syasuko.eckert@amd.comconst int NumCCRegs = NUM_CCREGS;
629921Syasuko.eckert@amd.com
639921Syasuko.eckert@amd.com#define ISA_HAS_CC_REGS
646319SN/A
659917Ssteve.reinhardt@amd.com// Each 128 bit xmm register is broken into two effective 64 bit registers.
669917Ssteve.reinhardt@amd.com// Add 8 for the indices that are mapped over the fp stack
676329Sgblack@eecs.umich.educonst int NumFloatRegs =
689917Ssteve.reinhardt@amd.com    NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
696315SN/A
706329Sgblack@eecs.umich.edu// These enumerate all the registers for dependence tracking.
716329Sgblack@eecs.umich.eduenum DependenceTags {
729918Ssteve.reinhardt@amd.com    // FP_Reg_Base must be large enough to be bigger than any integer
739917Ssteve.reinhardt@amd.com    // register index which has the IntFoldBit (1 << 6) set.  To be safe
749917Ssteve.reinhardt@amd.com    // we just start at (1 << 7) == 128.
759918Ssteve.reinhardt@amd.com    FP_Reg_Base = 128,
769920Syasuko.eckert@amd.com    CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
7710935Snilay@cs.wisc.edu    Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
789918Ssteve.reinhardt@amd.com    Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
796329Sgblack@eecs.umich.edu};
804137SN/A
8113610Sgiacomo.gabrielli@arm.comconst int NumVecRegs = 1;  // Not applicable to x86
8213610Sgiacomo.gabrielli@arm.com                           // (1 to prevent warnings)
8313610Sgiacomo.gabrielli@arm.comconst int NumVecPredRegs = 1;  // Not applicable to x86
8413610Sgiacomo.gabrielli@arm.com                               // (1 to prevent warnings)
8513610Sgiacomo.gabrielli@arm.com
866329Sgblack@eecs.umich.edu// semantically meaningful register indices
876329Sgblack@eecs.umich.edu//There is no such register in X86
886329Sgblack@eecs.umich.educonst int ZeroReg = NUM_INTREGS;
896329Sgblack@eecs.umich.educonst int StackPointerReg = INTREG_RSP;
906329Sgblack@eecs.umich.edu//X86 doesn't seem to have a link register
916329Sgblack@eecs.umich.educonst int ReturnAddressReg = 0;
926329Sgblack@eecs.umich.educonst int ReturnValueReg = INTREG_RAX;
936329Sgblack@eecs.umich.educonst int FramePointerReg = INTREG_RBP;
944137SN/A
956329Sgblack@eecs.umich.edu// Some OS syscalls use a second register (rdx) to return a second
966329Sgblack@eecs.umich.edu// value
976329Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = INTREG_RDX;
986329Sgblack@eecs.umich.edu
9913610Sgiacomo.gabrielli@arm.com// Not applicable to x86
10013610Sgiacomo.gabrielli@arm.comusing VecElem = ::DummyVecElem;
10113610Sgiacomo.gabrielli@arm.comusing VecReg = ::DummyVecReg;
10213610Sgiacomo.gabrielli@arm.comusing ConstVecReg = ::DummyConstVecReg;
10313610Sgiacomo.gabrielli@arm.comusing VecRegContainer = ::DummyVecRegContainer;
10413610Sgiacomo.gabrielli@arm.comconstexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
10513610Sgiacomo.gabrielli@arm.comconstexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
10613610Sgiacomo.gabrielli@arm.com
10713610Sgiacomo.gabrielli@arm.com// Not applicable to x86
10813610Sgiacomo.gabrielli@arm.comusing VecPredReg = ::DummyVecPredReg;
10913610Sgiacomo.gabrielli@arm.comusing ConstVecPredReg = ::DummyConstVecPredReg;
11013610Sgiacomo.gabrielli@arm.comusing VecPredRegContainer = ::DummyVecPredRegContainer;
11113610Sgiacomo.gabrielli@arm.comconstexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
11213610Sgiacomo.gabrielli@arm.comconstexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
11312109SRekai.GonzalezAlberquilla@arm.com
1147811Ssteve.reinhardt@amd.com} // namespace X86ISA
1154120SN/A
1164120SN/A#endif // __ARCH_X86_REGFILE_HH__
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