1/*
2 * Copyright (c) 2011, 2013, 2016-2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 *          Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <deque>
52#include <list>
53#include <string>
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/exec_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/inst_res.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/op_class.hh"
65#include "cpu/static_inst.hh"
66#include "cpu/translation.hh"
67#include "mem/packet.hh"
68#include "mem/request.hh"
69#include "sim/byteswap.hh"
70#include "sim/system.hh"
71
72/**
73 * @file
74 * Defines a dynamic instruction context.
75 */
76
77template <class Impl>
78class BaseDynInst : public ExecContext, public RefCounted
79{
80  public:
81    // Typedef for the CPU.
82    typedef typename Impl::CPUType ImplCPU;
83    typedef typename ImplCPU::ImplState ImplState;
84    using VecRegContainer = TheISA::VecRegContainer;
85
86    using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*;
87    using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator;
88    using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator;
89
90    // The DynInstPtr type.
91    typedef typename Impl::DynInstPtr DynInstPtr;
92    typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
93
94    // The list of instructions iterator type.
95    typedef typename std::list<DynInstPtr>::iterator ListIt;
96
97    enum {
98        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
99        MaxInstDestRegs = TheISA::MaxInstDestRegs       /// Max dest regs
100    };
101
102  protected:
103    enum Status {
104        IqEntry,                 /// Instruction is in the IQ
105        RobEntry,                /// Instruction is in the ROB
106        LsqEntry,                /// Instruction is in the LSQ
107        Completed,               /// Instruction has completed
108        ResultReady,             /// Instruction has its result
109        CanIssue,                /// Instruction can issue and execute
110        Issued,                  /// Instruction has issued
111        Executed,                /// Instruction has executed
112        CanCommit,               /// Instruction can commit
113        AtCommit,                /// Instruction has reached commit
114        Committed,               /// Instruction has committed
115        Squashed,                /// Instruction is squashed
116        SquashedInIQ,            /// Instruction is squashed in the IQ
117        SquashedInLSQ,           /// Instruction is squashed in the LSQ
118        SquashedInROB,           /// Instruction is squashed in the ROB
119        PinnedRegsRenamed,       /// Pinned registers are renamed
120        PinnedRegsWritten,       /// Pinned registers are written back
121        PinnedRegsSquashDone,    /// Regs pinning status updated after squash
122        RecoverInst,             /// Is a recover instruction
123        BlockingInst,            /// Is a blocking instruction
124        ThreadsyncWait,          /// Is a thread synchronization instruction
125        SerializeBefore,         /// Needs to serialize on
126                                 /// instructions ahead of it
127        SerializeAfter,          /// Needs to serialize instructions behind it
128        SerializeHandled,        /// Serialization has been handled
129        NumStatus
130    };
131
132    enum Flags {
133        NotAnInst,
134        TranslationStarted,
135        TranslationCompleted,
136        PossibleLoadViolation,
137        HitExternalSnoop,
138        EffAddrValid,
139        RecordResult,
140        Predicate,
141        MemAccPredicate,
142        PredTaken,
143        IsStrictlyOrdered,
144        ReqMade,
145        MemOpDone,
146        MaxFlags
147    };
148
149  public:
150    /** The sequence number of the instruction. */
151    InstSeqNum seqNum;
152
153    /** The StaticInst used by this BaseDynInst. */
154    const StaticInstPtr staticInst;
155
156    /** Pointer to the Impl's CPU object. */
157    ImplCPU *cpu;
158
159    BaseCPU *getCpuPtr() { return cpu; }
160
161    /** Pointer to the thread state. */
162    ImplState *thread;
163
164    /** The kind of fault this instruction has generated. */
165    Fault fault;
166
167    /** InstRecord that tracks this instructions. */
168    Trace::InstRecord *traceData;
169
170  protected:
171    /** The result of the instruction; assumes an instruction can have many
172     *  destination registers.
173     */
174    std::queue<InstResult> instResult;
175
176    /** PC state for this instruction. */
177    TheISA::PCState pc;
178
179  private:
180    /* An amalgamation of a lot of boolean values into one */
181    std::bitset<MaxFlags> instFlags;
182
183    /** The status of this BaseDynInst.  Several bits can be set. */
184    std::bitset<NumStatus> status;
185
186  protected:
187     /** Whether or not the source register is ready.
188     *  @todo: Not sure this should be here vs the derived class.
189     */
190    std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
191
192  public:
193    /** The thread this instruction is from. */
194    ThreadID threadNumber;
195
196    /** Iterator pointing to this BaseDynInst in the list of all insts. */
197    ListIt instListIt;
198
199    ////////////////////// Branch Data ///////////////
200    /** Predicted PC state after this instruction. */
201    TheISA::PCState predPC;
202
203    /** The Macroop if one exists */
204    const StaticInstPtr macroop;
205
206    /** How many source registers are ready. */
207    uint8_t readyRegs;
208
209  public:
210    /////////////////////// Load Store Data //////////////////////
211    /** The effective virtual address (lds & stores only). */
212    Addr effAddr;
213
214    /** The effective physical address. */
215    Addr physEffAddr;
216
217    /** The memory request flags (from translation). */
218    unsigned memReqFlags;
219
220    /** data address space ID, for loads & stores. */
221    short asid;
222
223    /** The size of the request */
224    unsigned effSize;
225
226    /** Pointer to the data for the memory access. */
227    uint8_t *memData;
228
229    /** Load queue index. */
230    int16_t lqIdx;
231    LQIterator lqIt;
232
233    /** Store queue index. */
234    int16_t sqIdx;
235    SQIterator sqIt;
236
237
238    /////////////////////// TLB Miss //////////////////////
239    /**
240     * Saved memory request (needed when the DTB address translation is
241     * delayed due to a hw page table walk).
242     */
243    LSQRequestPtr savedReq;
244
245    /////////////////////// Checker //////////////////////
246    // Need a copy of main request pointer to verify on writes.
247    RequestPtr reqToVerify;
248
249  protected:
250    /** Flattened register index of the destination registers of this
251     *  instruction.
252     */
253    std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
254
255    /** Physical register index of the destination registers of this
256     *  instruction.
257     */
258    std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;
259
260    /** Physical register index of the source registers of this
261     *  instruction.
262     */
263    std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;
264
265    /** Physical register index of the previous producers of the
266     *  architected destinations.
267     */
268    std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;
269
270
271  public:
272    /** Records changes to result? */
273    void recordResult(bool f) { instFlags[RecordResult] = f; }
274
275    /** Is the effective virtual address valid. */
276    bool effAddrValid() const { return instFlags[EffAddrValid]; }
277    void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }
278
279    /** Whether or not the memory operation is done. */
280    bool memOpDone() const { return instFlags[MemOpDone]; }
281    void memOpDone(bool f) { instFlags[MemOpDone] = f; }
282
283    bool notAnInst() const { return instFlags[NotAnInst]; }
284    void setNotAnInst() { instFlags[NotAnInst] = true; }
285
286
287    ////////////////////////////////////////////
288    //
289    // INSTRUCTION EXECUTION
290    //
291    ////////////////////////////////////////////
292
293    void demapPage(Addr vaddr, uint64_t asn)
294    {
295        cpu->demapPage(vaddr, asn);
296    }
297    void demapInstPage(Addr vaddr, uint64_t asn)
298    {
299        cpu->demapPage(vaddr, asn);
300    }
301    void demapDataPage(Addr vaddr, uint64_t asn)
302    {
303        cpu->demapPage(vaddr, asn);
304    }
305
306    Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
307            const std::vector<bool>& byteEnable = std::vector<bool>());
308
309    Fault writeMem(uint8_t *data, unsigned size, Addr addr,
310                   Request::Flags flags, uint64_t *res,
311                   const std::vector<bool>& byteEnable = std::vector<bool>());
312
313    Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
314                         AtomicOpFunctorPtr amo_op);
315
316    /** True if the DTB address translation has started. */
317    bool translationStarted() const { return instFlags[TranslationStarted]; }
318    void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
319
320    /** True if the DTB address translation has completed. */
321    bool translationCompleted() const { return instFlags[TranslationCompleted]; }
322    void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
323
324    /** True if this address was found to match a previous load and they issued
325     * out of order. If that happend, then it's only a problem if an incoming
326     * snoop invalidate modifies the line, in which case we need to squash.
327     * If nothing modified the line the order doesn't matter.
328     */
329    bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
330    void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
331
332    /** True if the address hit a external snoop while sitting in the LSQ.
333     * If this is true and a older instruction sees it, this instruction must
334     * reexecute
335     */
336    bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
337    void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
338
339    /**
340     * Returns true if the DTB address translation is being delayed due to a hw
341     * page table walk.
342     */
343    bool isTranslationDelayed() const
344    {
345        return (translationStarted() && !translationCompleted());
346    }
347
348  public:
349#ifdef DEBUG
350    void dumpSNList();
351#endif
352
353    /** Returns the physical register index of the i'th destination
354     *  register.
355     */
356    PhysRegIdPtr renamedDestRegIdx(int idx) const
357    {
358        return _destRegIdx[idx];
359    }
360
361    /** Returns the physical register index of the i'th source register. */
362    PhysRegIdPtr renamedSrcRegIdx(int idx) const
363    {
364        assert(TheISA::MaxInstSrcRegs > idx);
365        return _srcRegIdx[idx];
366    }
367
368    /** Returns the flattened register index of the i'th destination
369     *  register.
370     */
371    const RegId& flattenedDestRegIdx(int idx) const
372    {
373        return _flatDestRegIdx[idx];
374    }
375
376    /** Returns the physical register index of the previous physical register
377     *  that remapped to the same logical register index.
378     */
379    PhysRegIdPtr prevDestRegIdx(int idx) const
380    {
381        return _prevDestRegIdx[idx];
382    }
383
384    /** Renames a destination register to a physical register.  Also records
385     *  the previous physical register that the logical register mapped to.
386     */
387    void renameDestReg(int idx,
388                       PhysRegIdPtr renamed_dest,
389                       PhysRegIdPtr previous_rename)
390    {
391        _destRegIdx[idx] = renamed_dest;
392        _prevDestRegIdx[idx] = previous_rename;
393        if (renamed_dest->isPinned())
394            setPinnedRegsRenamed();
395    }
396
397    /** Renames a source logical register to the physical register which
398     *  has/will produce that logical register's result.
399     *  @todo: add in whether or not the source register is ready.
400     */
401    void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
402    {
403        _srcRegIdx[idx] = renamed_src;
404    }
405
406    /** Flattens a destination architectural register index into a logical
407     * index.
408     */
409    void flattenDestReg(int idx, const RegId& flattened_dest)
410    {
411        _flatDestRegIdx[idx] = flattened_dest;
412    }
413    /** BaseDynInst constructor given a binary instruction.
414     *  @param staticInst A StaticInstPtr to the underlying instruction.
415     *  @param pc The PC state for the instruction.
416     *  @param predPC The predicted next PC state for the instruction.
417     *  @param seq_num The sequence number of the instruction.
418     *  @param cpu Pointer to the instruction's CPU.
419     */
420    BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
421                TheISA::PCState pc, TheISA::PCState predPC,
422                InstSeqNum seq_num, ImplCPU *cpu);
423
424    /** BaseDynInst constructor given a StaticInst pointer.
425     *  @param _staticInst The StaticInst for this BaseDynInst.
426     */
427    BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop);
428
429    /** BaseDynInst destructor. */
430    ~BaseDynInst();
431
432  private:
433    /** Function to initialize variables in the constructors. */
434    void initVars();
435
436  public:
437    /** Dumps out contents of this BaseDynInst. */
438    void dump();
439
440    /** Dumps out contents of this BaseDynInst into given string. */
441    void dump(std::string &outstring);
442
443    /** Read this CPU's ID. */
444    int cpuId() const { return cpu->cpuId(); }
445
446    /** Read this CPU's Socket ID. */
447    uint32_t socketId() const { return cpu->socketId(); }
448
449    /** Read this CPU's data requestor ID */
450    MasterID masterId() const { return cpu->dataMasterId(); }
451
452    /** Read this context's system-wide ID **/
453    ContextID contextId() const { return thread->contextId(); }
454
455    /** Returns the fault type. */
456    Fault getFault() const { return fault; }
457    /** TODO: This I added for the LSQRequest side to be able to modify the
458     * fault. There should be a better mechanism in place. */
459    Fault& getFault() { return fault; }
460
461    /** Checks whether or not this instruction has had its branch target
462     *  calculated yet.  For now it is not utilized and is hacked to be
463     *  always false.
464     *  @todo: Actually use this instruction.
465     */
466    bool doneTargCalc() { return false; }
467
468    /** Set the predicted target of this current instruction. */
469    void setPredTarg(const TheISA::PCState &_predPC)
470    {
471        predPC = _predPC;
472    }
473
474    const TheISA::PCState &readPredTarg() { return predPC; }
475
476    /** Returns the predicted PC immediately after the branch. */
477    Addr predInstAddr() { return predPC.instAddr(); }
478
479    /** Returns the predicted PC two instructions after the branch */
480    Addr predNextInstAddr() { return predPC.nextInstAddr(); }
481
482    /** Returns the predicted micro PC after the branch */
483    Addr predMicroPC() { return predPC.microPC(); }
484
485    /** Returns whether the instruction was predicted taken or not. */
486    bool readPredTaken()
487    {
488        return instFlags[PredTaken];
489    }
490
491    void setPredTaken(bool predicted_taken)
492    {
493        instFlags[PredTaken] = predicted_taken;
494    }
495
496    /** Returns whether the instruction mispredicted. */
497    bool mispredicted()
498    {
499        TheISA::PCState tempPC = pc;
500        TheISA::advancePC(tempPC, staticInst);
501        return !(tempPC == predPC);
502    }
503
504    //
505    //  Instruction types.  Forward checks to StaticInst object.
506    //
507    bool isNop()          const { return staticInst->isNop(); }
508    bool isMemRef()       const { return staticInst->isMemRef(); }
509    bool isLoad()         const { return staticInst->isLoad(); }
510    bool isStore()        const { return staticInst->isStore(); }
511    bool isAtomic()       const { return staticInst->isAtomic(); }
512    bool isStoreConditional() const
513    { return staticInst->isStoreConditional(); }
514    bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
515    bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
516    bool isInteger()      const { return staticInst->isInteger(); }
517    bool isFloating()     const { return staticInst->isFloating(); }
518    bool isVector()       const { return staticInst->isVector(); }
519    bool isControl()      const { return staticInst->isControl(); }
520    bool isCall()         const { return staticInst->isCall(); }
521    bool isReturn()       const { return staticInst->isReturn(); }
522    bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
523    bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
524    bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
525    bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
526    bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
527    bool isThreadSync()   const { return staticInst->isThreadSync(); }
528    bool isSerializing()  const { return staticInst->isSerializing(); }
529    bool isSerializeBefore() const
530    { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
531    bool isSerializeAfter() const
532    { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
533    bool isSquashAfter() const { return staticInst->isSquashAfter(); }
534    bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
535    bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
536    bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
537    bool isQuiesce() const { return staticInst->isQuiesce(); }
538    bool isIprAccess() const { return staticInst->isIprAccess(); }
539    bool isUnverifiable() const { return staticInst->isUnverifiable(); }
540    bool isSyscall() const { return staticInst->isSyscall(); }
541    bool isMacroop() const { return staticInst->isMacroop(); }
542    bool isMicroop() const { return staticInst->isMicroop(); }
543    bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
544    bool isLastMicroop() const { return staticInst->isLastMicroop(); }
545    bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
546    bool isMicroBranch() const { return staticInst->isMicroBranch(); }
547
548    /** Temporarily sets this instruction as a serialize before instruction. */
549    void setSerializeBefore() { status.set(SerializeBefore); }
550
551    /** Clears the serializeBefore part of this instruction. */
552    void clearSerializeBefore() { status.reset(SerializeBefore); }
553
554    /** Checks if this serializeBefore is only temporarily set. */
555    bool isTempSerializeBefore() { return status[SerializeBefore]; }
556
557    /** Temporarily sets this instruction as a serialize after instruction. */
558    void setSerializeAfter() { status.set(SerializeAfter); }
559
560    /** Clears the serializeAfter part of this instruction.*/
561    void clearSerializeAfter() { status.reset(SerializeAfter); }
562
563    /** Checks if this serializeAfter is only temporarily set. */
564    bool isTempSerializeAfter() { return status[SerializeAfter]; }
565
566    /** Sets the serialization part of this instruction as handled. */
567    void setSerializeHandled() { status.set(SerializeHandled); }
568
569    /** Checks if the serialization part of this instruction has been
570     *  handled.  This does not apply to the temporary serializing
571     *  state; it only applies to this instruction's own permanent
572     *  serializing state.
573     */
574    bool isSerializeHandled() { return status[SerializeHandled]; }
575
576    /** Returns the opclass of this instruction. */
577    OpClass opClass() const { return staticInst->opClass(); }
578
579    /** Returns the branch target address. */
580    TheISA::PCState branchTarget() const
581    { return staticInst->branchTarget(pc); }
582
583    /** Returns the number of source registers. */
584    int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
585
586    /** Returns the number of destination registers. */
587    int8_t numDestRegs() const { return staticInst->numDestRegs(); }
588
589    // the following are used to track physical register usage
590    // for machines with separate int & FP reg files
591    int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
592    int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
593    int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
594    int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
595    int8_t numVecElemDestRegs() const
596    {
597        return staticInst->numVecElemDestRegs();
598    }
599    int8_t
600    numVecPredDestRegs() const
601    {
602        return staticInst->numVecPredDestRegs();
603    }
604
605    /** Returns the logical register index of the i'th destination register. */
606    const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
607
608    /** Returns the logical register index of the i'th source register. */
609    const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
610
611    /** Return the size of the instResult queue. */
612    uint8_t resultSize() { return instResult.size(); }
613
614    /** Pops a result off the instResult queue.
615     * If the result stack is empty, return the default value.
616     * */
617    InstResult popResult(InstResult dflt = InstResult())
618    {
619        if (!instResult.empty()) {
620            InstResult t = instResult.front();
621            instResult.pop();
622            return t;
623        }
624        return dflt;
625    }
626
627    /** Pushes a result onto the instResult queue. */
628    /** @{ */
629    /** Scalar result. */
630    template<typename T>
631    void setScalarResult(T&& t)
632    {
633        if (instFlags[RecordResult]) {
634            instResult.push(InstResult(std::forward<T>(t),
635                        InstResult::ResultType::Scalar));
636        }
637    }
638
639    /** Full vector result. */
640    template<typename T>
641    void setVecResult(T&& t)
642    {
643        if (instFlags[RecordResult]) {
644            instResult.push(InstResult(std::forward<T>(t),
645                        InstResult::ResultType::VecReg));
646        }
647    }
648
649    /** Vector element result. */
650    template<typename T>
651    void setVecElemResult(T&& t)
652    {
653        if (instFlags[RecordResult]) {
654            instResult.push(InstResult(std::forward<T>(t),
655                        InstResult::ResultType::VecElem));
656        }
657    }
658
659    /** Predicate result. */
660    template<typename T>
661    void setVecPredResult(T&& t)
662    {
663        if (instFlags[RecordResult]) {
664            instResult.push(InstResult(std::forward<T>(t),
665                            InstResult::ResultType::VecPredReg));
666        }
667    }
668    /** @} */
669
670    /** Records an integer register being set to a value. */
671    void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
672    {
673        setScalarResult(val);
674    }
675
676    /** Records a CC register being set to a value. */
677    void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
678    {
679        setScalarResult(val);
680    }
681
682    /** Record a vector register being set to a value */
683    void setVecRegOperand(const StaticInst *si, int idx,
684            const VecRegContainer& val)
685    {
686        setVecResult(val);
687    }
688
689    /** Records an fp register being set to an integer value. */
690    void
691    setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
692    {
693        setScalarResult(val);
694    }
695
696    /** Record a vector register being set to a value */
697    void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
698    {
699        setVecElemResult(val);
700    }
701
702    /** Record a vector register being set to a value */
703    void setVecPredRegOperand(const StaticInst *si, int idx,
704                              const VecPredRegContainer& val)
705    {
706        setVecPredResult(val);
707    }
708
709    /** Records that one of the source registers is ready. */
710    void markSrcRegReady();
711
712    /** Marks a specific register as ready. */
713    void markSrcRegReady(RegIndex src_idx);
714
715    /** Returns if a source register is ready. */
716    bool isReadySrcRegIdx(int idx) const
717    {
718        return this->_readySrcRegIdx[idx];
719    }
720
721    /** Sets this instruction as completed. */
722    void setCompleted() { status.set(Completed); }
723
724    /** Returns whether or not this instruction is completed. */
725    bool isCompleted() const { return status[Completed]; }
726
727    /** Marks the result as ready. */
728    void setResultReady() { status.set(ResultReady); }
729
730    /** Returns whether or not the result is ready. */
731    bool isResultReady() const { return status[ResultReady]; }
732
733    /** Sets this instruction as ready to issue. */
734    void setCanIssue() { status.set(CanIssue); }
735
736    /** Returns whether or not this instruction is ready to issue. */
737    bool readyToIssue() const { return status[CanIssue]; }
738
739    /** Clears this instruction being able to issue. */
740    void clearCanIssue() { status.reset(CanIssue); }
741
742    /** Sets this instruction as issued from the IQ. */
743    void setIssued() { status.set(Issued); }
744
745    /** Returns whether or not this instruction has issued. */
746    bool isIssued() const { return status[Issued]; }
747
748    /** Clears this instruction as being issued. */
749    void clearIssued() { status.reset(Issued); }
750
751    /** Sets this instruction as executed. */
752    void setExecuted() { status.set(Executed); }
753
754    /** Returns whether or not this instruction has executed. */
755    bool isExecuted() const { return status[Executed]; }
756
757    /** Sets this instruction as ready to commit. */
758    void setCanCommit() { status.set(CanCommit); }
759
760    /** Clears this instruction as being ready to commit. */
761    void clearCanCommit() { status.reset(CanCommit); }
762
763    /** Returns whether or not this instruction is ready to commit. */
764    bool readyToCommit() const { return status[CanCommit]; }
765
766    void setAtCommit() { status.set(AtCommit); }
767
768    bool isAtCommit() { return status[AtCommit]; }
769
770    /** Sets this instruction as committed. */
771    void setCommitted() { status.set(Committed); }
772
773    /** Returns whether or not this instruction is committed. */
774    bool isCommitted() const { return status[Committed]; }
775
776    /** Sets this instruction as squashed. */
777    void setSquashed();
778
779    /** Returns whether or not this instruction is squashed. */
780    bool isSquashed() const { return status[Squashed]; }
781
782    //Instruction Queue Entry
783    //-----------------------
784    /** Sets this instruction as a entry the IQ. */
785    void setInIQ() { status.set(IqEntry); }
786
787    /** Sets this instruction as a entry the IQ. */
788    void clearInIQ() { status.reset(IqEntry); }
789
790    /** Returns whether or not this instruction has issued. */
791    bool isInIQ() const { return status[IqEntry]; }
792
793    /** Sets this instruction as squashed in the IQ. */
794    void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
795
796    /** Returns whether or not this instruction is squashed in the IQ. */
797    bool isSquashedInIQ() const { return status[SquashedInIQ]; }
798
799
800    //Load / Store Queue Functions
801    //-----------------------
802    /** Sets this instruction as a entry the LSQ. */
803    void setInLSQ() { status.set(LsqEntry); }
804
805    /** Sets this instruction as a entry the LSQ. */
806    void removeInLSQ() { status.reset(LsqEntry); }
807
808    /** Returns whether or not this instruction is in the LSQ. */
809    bool isInLSQ() const { return status[LsqEntry]; }
810
811    /** Sets this instruction as squashed in the LSQ. */
812    void setSquashedInLSQ() { status.set(SquashedInLSQ); status.set(Squashed);}
813
814    /** Returns whether or not this instruction is squashed in the LSQ. */
815    bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
816
817
818    //Reorder Buffer Functions
819    //-----------------------
820    /** Sets this instruction as a entry the ROB. */
821    void setInROB() { status.set(RobEntry); }
822
823    /** Sets this instruction as a entry the ROB. */
824    void clearInROB() { status.reset(RobEntry); }
825
826    /** Returns whether or not this instruction is in the ROB. */
827    bool isInROB() const { return status[RobEntry]; }
828
829    /** Sets this instruction as squashed in the ROB. */
830    void setSquashedInROB() { status.set(SquashedInROB); }
831
832    /** Returns whether or not this instruction is squashed in the ROB. */
833    bool isSquashedInROB() const { return status[SquashedInROB]; }
834
835    /** Returns whether pinned registers are renamed */
836    bool isPinnedRegsRenamed() const { return status[PinnedRegsRenamed]; }
837
838    /** Sets the destination registers as renamed */
839    void
840    setPinnedRegsRenamed()
841    {
842        assert(!status[PinnedRegsSquashDone]);
843        assert(!status[PinnedRegsWritten]);
844        status.set(PinnedRegsRenamed);
845    }
846
847    /** Returns whether destination registers are written */
848    bool isPinnedRegsWritten() const { return status[PinnedRegsWritten]; }
849
850    /** Sets destination registers as written */
851    void
852    setPinnedRegsWritten()
853    {
854        assert(!status[PinnedRegsSquashDone]);
855        assert(status[PinnedRegsRenamed]);
856        status.set(PinnedRegsWritten);
857    }
858
859    /** Return whether dest registers' pinning status updated after squash */
860    bool
861    isPinnedRegsSquashDone() const { return status[PinnedRegsSquashDone]; }
862
863    /** Sets dest registers' status updated after squash */
864    void
865    setPinnedRegsSquashDone() {
866        assert(!status[PinnedRegsSquashDone]);
867        status.set(PinnedRegsSquashDone);
868    }
869
870    /** Read the PC state of this instruction. */
871    TheISA::PCState pcState() const { return pc; }
872
873    /** Set the PC state of this instruction. */
874    void pcState(const TheISA::PCState &val) { pc = val; }
875
876    /** Read the PC of this instruction. */
877    Addr instAddr() const { return pc.instAddr(); }
878
879    /** Read the PC of the next instruction. */
880    Addr nextInstAddr() const { return pc.nextInstAddr(); }
881
882    /**Read the micro PC of this instruction. */
883    Addr microPC() const { return pc.microPC(); }
884
885    bool readPredicate() const
886    {
887        return instFlags[Predicate];
888    }
889
890    void setPredicate(bool val)
891    {
892        instFlags[Predicate] = val;
893
894        if (traceData) {
895            traceData->setPredicate(val);
896        }
897    }
898
899    bool
900    readMemAccPredicate() const
901    {
902        return instFlags[MemAccPredicate];
903    }
904
905    void
906    setMemAccPredicate(bool val)
907    {
908        instFlags[MemAccPredicate] = val;
909    }
910
911    /** Sets the ASID. */
912    void setASID(short addr_space_id) { asid = addr_space_id; }
913    short getASID() { return asid; }
914
915    /** Sets the thread id. */
916    void setTid(ThreadID tid) { threadNumber = tid; }
917
918    /** Sets the pointer to the thread state. */
919    void setThreadState(ImplState *state) { thread = state; }
920
921    /** Returns the thread context. */
922    ThreadContext *tcBase() { return thread->getTC(); }
923
924  public:
925    /** Returns whether or not the eff. addr. source registers are ready. */
926    bool eaSrcsReady() const;
927
928    /** Is this instruction's memory access strictly ordered? */
929    bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
930    void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; }
931
932    /** Has this instruction generated a memory request. */
933    bool hasRequest() const { return instFlags[ReqMade]; }
934    /** Assert this instruction has generated a memory request. */
935    void setRequest() { instFlags[ReqMade] = true; }
936
937    /** Returns iterator to this instruction in the list of all insts. */
938    ListIt &getInstListIt() { return instListIt; }
939
940    /** Sets iterator for this instruction in the list of all insts. */
941    void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
942
943  public:
944    /** Returns the number of consecutive store conditional failures. */
945    unsigned int readStCondFailures() const
946    { return thread->storeCondFailures; }
947
948    /** Sets the number of consecutive store conditional failures. */
949    void setStCondFailures(unsigned int sc_failures)
950    { thread->storeCondFailures = sc_failures; }
951
952  public:
953    // monitor/mwait funtions
954    void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
955    bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
956    void mwaitAtomic(ThreadContext *tc)
957    { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
958    AddressMonitor *getAddrMonitor()
959    { return cpu->getCpuAddrMonitor(threadNumber); }
960};
961
962template<class Impl>
963Fault
964BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
965                                   Request::Flags flags,
966                                   const std::vector<bool>& byteEnable)
967{
968    return cpu->pushRequest(
969            dynamic_cast<typename DynInstPtr::PtrType>(this),
970            /* ld */ true, nullptr, size, addr, flags, nullptr, nullptr,
971            byteEnable);
972}
973
974template<class Impl>
975Fault
976BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
977                            Request::Flags flags, uint64_t *res,
978                            const std::vector<bool>& byteEnable)
979{
980    return cpu->pushRequest(
981            dynamic_cast<typename DynInstPtr::PtrType>(this),
982            /* st */ false, data, size, addr, flags, res, nullptr, byteEnable);
983}
984
985template<class Impl>
986Fault
987BaseDynInst<Impl>::initiateMemAMO(Addr addr, unsigned size,
988                                  Request::Flags flags,
989                                  AtomicOpFunctorPtr amo_op)
990{
991    // atomic memory instructions do not have data to be written to memory yet
992    // since the atomic operations will be executed directly in cache/memory.
993    // Therefore, its `data` field is nullptr.
994    // Atomic memory requests need to carry their `amo_op` fields to cache/
995    // memory
996    return cpu->pushRequest(
997            dynamic_cast<typename DynInstPtr::PtrType>(this),
998            /* atomic */ false, nullptr, size, addr, flags, nullptr,
999            std::move(amo_op));
1000}
1001
1002#endif // __CPU_BASE_DYN_INST_HH__
1003