| /gem5/configs/common/ |
| H A D | Caches.py | 53 class L1Cache(Cache):
69 class L2Cache(Cache):
78 class IOCache(Cache):
87 class PageTableWalkerCache(Cache):
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| /gem5/src/mem/cache/ |
| H A D | cache.cc | 52 * Cache definitions.
63 #include "debug/Cache.hh"
72 #include "params/Cache.hh"
74 Cache::Cache(const CacheParams *p) function in class:Cache
81 Cache::satisfyRequest(PacketPtr pkt, CacheBlk *blk,
164 Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
175 DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());
193 Cache::doWritebacks(PacketList& writebacks, Tick forward_time)
235 Cache
[all...] |
| H A D | cache.hh | 69 class Cache : public BaseCache class in inherits:BaseCache
132 * @param blk Cache block being snooped
164 Cache(const CacheParams *p);
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| H A D | noncoherent_cache.cc | 52 * Cache definitions.
62 #include "debug/Cache.hh"
167 DPRINTF(Cache, "%s created %s from %s\n", __func__, pkt->print(),
179 DPRINTF(Cache, "Sending an atomic %s\n", bus_pkt->print());
193 DPRINTF(Cache, "Receive response: %s\n", bus_pkt->print());
198 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
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| H A D | Cache.py | 108 compressor = Param.BaseCacheCompressor(NULL, "Cache compressor.")
147 class Cache(BaseCache): class in inherits:BaseCache
148 type = 'Cache'
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| H A D | mshr.cc | 59 #include "debug/Cache.hh"
146 DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
149 DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
152 DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
373 DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());
432 // matching the conditions checked in Cache::handleSnoop
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| H A D | base.cc | 53 #include "debug/Cache.hh"
184 fatal("Cache ports on %s are not connected\n", name());
229 DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__,
272 DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__,
416 DPRINTF(Cache, "%s: Cache received %s with error\n", __func__,
420 DPRINTF(Cache, "%s: Handling response %s\n", __func__,
470 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
1038 DPRINTF(Cache, "
[all...] |
| H A D | base.hh | 63 #include "debug/Cache.hh"
693 * @param blk Cache block that the packet hit
1108 DPRINTF(Cache, "Potential to merge writeback %s", pkt->print());
1143 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
1157 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
1221 * Cache block visitor that writes back dirty cache blocks using
1227 * Cache block visitor that invalidates all blocks in the cache.
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| /gem5/configs/learning_gem5/part1/ |
| H A D | caches.py | 41 from m5.objects import Cache
51 class L1Cache(Cache):
52 """Simple L1 Cache with default values"""
112 class L2Cache(Cache):
113 """Simple L2 Cache with default values"""
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| /gem5/configs/common/cores/arm/ |
| H A D | ex5_LITTLE.py | 101 class L1Cache(Cache):
122 # TLB Cache
124 class WalkCache(Cache):
137 # L2 Cache
138 class L2(Cache):
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| H A D | O3_ARM_v7a.py | 151 # Instruction Cache
152 class O3_ARM_v7a_ICache(Cache):
164 # Data Cache
165 class O3_ARM_v7a_DCache(Cache):
177 # TLB Cache
179 class O3_ARM_v7aWalkCache(Cache):
192 # L2 Cache
193 class O3_ARM_v7aL2(Cache):
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| H A D | ex5_big.py | 152 class L1Cache(Cache):
160 # Instruction Cache
167 # Data Cache
174 # TLB Cache
176 class WalkCache(Cache):
189 # L2 Cache
190 class L2(Cache):
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| H A D | HPI.py | 1343 class HPI_WalkCache(Cache):
1366 class HPI_ICache(Cache):
1376 class HPI_DCache(Cache):
1389 class HPI_L2(Cache):
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| /gem5/configs/example/arm/ |
| H A D | fs_power.py | 74 # Example to report l2 Cache overall_accesses
113 # Example power model for the L2 Cache of the bigCluster
115 if not isinstance(l2, m5.objects.Cache):
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| H A D | devices.py | 96 class L3(Cache):
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| /gem5/tests/gem5/cpu_tests/ |
| H A D | run.py | 36 class L1Cache(Cache):
37 """Simple L1 Cache with default values"""
75 class L2Cache(Cache):
76 """Simple L2 Cache with default values"""
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| /gem5/configs/splash2/ |
| H A D | run.py | 159 # Base L1 Cache Definition
162 class L1(Cache):
168 # Base L2 Cache Definition
171 class L2(Cache):
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| H A D | cluster.py | 138 # Base L1 Cache Definition
141 class L1(Cache):
147 # Base L2 Cache Definition
150 class L2(Cache):
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| /gem5/configs/example/ |
| H A D | memtest.py | 183 proto_l1 = Cache(size = '32kB', assoc = 4,
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| H A D | memcheck.py | 169 proto_l1 = Cache(size = '32kB', assoc = 4,
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| /gem5/configs/dram/ |
| H A D | lat_mem_rd.py | 268 class L3Cache(Cache):
|