12810SN/A/* 213932Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2018-2019 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 4112724Snikos.nikoleris@arm.com * Nikos Nikoleris 422810SN/A */ 432810SN/A 442810SN/A/** 452810SN/A * @file 462810SN/A * Definition of BaseCache functions. 472810SN/A */ 482810SN/A 4911486Snikos.nikoleris@arm.com#include "mem/cache/base.hh" 5011486Snikos.nikoleris@arm.com 5112724Snikos.nikoleris@arm.com#include "base/compiler.hh" 5212724Snikos.nikoleris@arm.com#include "base/logging.hh" 538232Snate@binkert.org#include "debug/Cache.hh" 5413947Sodanrc@yahoo.com.br#include "debug/CacheComp.hh" 5512724Snikos.nikoleris@arm.com#include "debug/CachePort.hh" 5613222Sodanrc@yahoo.com.br#include "debug/CacheRepl.hh" 5712724Snikos.nikoleris@arm.com#include "debug/CacheVerbose.hh" 5813945Sodanrc@yahoo.com.br#include "mem/cache/compressors/base.hh" 5911486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh" 6012724Snikos.nikoleris@arm.com#include "mem/cache/prefetch/base.hh" 6112724Snikos.nikoleris@arm.com#include "mem/cache/queue_entry.hh" 6213947Sodanrc@yahoo.com.br#include "mem/cache/tags/super_blk.hh" 6312724Snikos.nikoleris@arm.com#include "params/BaseCache.hh" 6413352Snikos.nikoleris@arm.com#include "params/WriteAllocator.hh" 6512724Snikos.nikoleris@arm.com#include "sim/core.hh" 6612724Snikos.nikoleris@arm.com 672810SN/Ausing namespace std; 682810SN/A 698856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 708856Sandreas.hansson@arm.com BaseCache *_cache, 718856Sandreas.hansson@arm.com const std::string &_label) 7213564Snikos.nikoleris@arm.com : QueuedSlavePort(_name, _cache, queue), 7313564Snikos.nikoleris@arm.com queue(*_cache, *this, true, _label), 7412084Sspwilson2@wisc.edu blocked(false), mustSendRetry(false), 7512084Sspwilson2@wisc.edu sendRetryEvent([this]{ processSendRetry(); }, _name) 768856Sandreas.hansson@arm.com{ 778856Sandreas.hansson@arm.com} 784475SN/A 7911053Sandreas.hansson@arm.comBaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 8013892Sgabeblack@google.com : ClockedObject(p), 8112724Snikos.nikoleris@arm.com cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"), 8212724Snikos.nikoleris@arm.com memSidePort(p->name + ".mem_side", this, "MemSidePort"), 8311377Sandreas.hansson@arm.com mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below 8411377Sandreas.hansson@arm.com writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below 8512724Snikos.nikoleris@arm.com tags(p->tags), 8613945Sodanrc@yahoo.com.br compressor(p->compressor), 8712724Snikos.nikoleris@arm.com prefetcher(p->prefetcher), 8813352Snikos.nikoleris@arm.com writeAllocator(p->write_allocator), 8912724Snikos.nikoleris@arm.com writebackClean(p->writeback_clean), 9012724Snikos.nikoleris@arm.com tempBlockWriteback(nullptr), 9112724Snikos.nikoleris@arm.com writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 9212724Snikos.nikoleris@arm.com name(), false, 9312724Snikos.nikoleris@arm.com EventBase::Delayed_Writeback_Pri), 9411053Sandreas.hansson@arm.com blkSize(blk_size), 9511722Ssophiane.senni@gmail.com lookupLatency(p->tag_latency), 9611722Ssophiane.senni@gmail.com dataLatency(p->data_latency), 9711722Ssophiane.senni@gmail.com forwardLatency(p->tag_latency), 9811722Ssophiane.senni@gmail.com fillLatency(p->data_latency), 999263Smrinmoy.ghosh@arm.com responseLatency(p->response_latency), 10013418Sodanrc@yahoo.com.br sequentialAccess(p->sequential_access), 1015034SN/A numTarget(p->tgts_per_mshr), 10211331Sandreas.hansson@arm.com forwardSnoops(true), 10312724Snikos.nikoleris@arm.com clusivity(p->clusivity), 10410884Sandreas.hansson@arm.com isReadOnly(p->is_read_only), 1054626SN/A blocked(0), 10610360Sandreas.hansson@arm.com order(0), 10711484Snikos.nikoleris@arm.com noTargetMSHR(nullptr), 1085034SN/A missCount(p->max_miss_count), 1098883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 1108833Sdam.sunwoo@arm.com system(p->system) 1114458SN/A{ 11211377Sandreas.hansson@arm.com // the MSHR queue has no reserve entries as we check the MSHR 11311377Sandreas.hansson@arm.com // queue on every single allocation, whereas the write queue has 11411377Sandreas.hansson@arm.com // as many reserve entries as we have MSHRs, since every MSHR may 11511377Sandreas.hansson@arm.com // eventually require a writeback, and we do not check the write 11611377Sandreas.hansson@arm.com // buffer before committing to an MSHR 11711377Sandreas.hansson@arm.com 11811331Sandreas.hansson@arm.com // forward snoops is overridden in init() once we can query 11911331Sandreas.hansson@arm.com // whether the connected master is actually snooping or not 12012724Snikos.nikoleris@arm.com 12112843Srmk35@cl.cam.ac.uk tempBlock = new TempCacheBlk(blkSize); 12212724Snikos.nikoleris@arm.com 12313419Sodanrc@yahoo.com.br tags->tagsInit(); 12412724Snikos.nikoleris@arm.com if (prefetcher) 12512724Snikos.nikoleris@arm.com prefetcher->setCache(this); 12612724Snikos.nikoleris@arm.com} 12712724Snikos.nikoleris@arm.com 12812724Snikos.nikoleris@arm.comBaseCache::~BaseCache() 12912724Snikos.nikoleris@arm.com{ 13012724Snikos.nikoleris@arm.com delete tempBlock; 1312810SN/A} 1322810SN/A 1333013SN/Avoid 1348856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 1352810SN/A{ 1363013SN/A assert(!blocked); 13710714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is blocking new requests\n"); 1382810SN/A blocked = true; 1399614Srene.dejong@arm.com // if we already scheduled a retry in this cycle, but it has not yet 1409614Srene.dejong@arm.com // happened, cancel it 1419614Srene.dejong@arm.com if (sendRetryEvent.scheduled()) { 14210345SCurtis.Dunham@arm.com owner.deschedule(sendRetryEvent); 14310714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port descheduled retry\n"); 14410345SCurtis.Dunham@arm.com mustSendRetry = true; 1459614Srene.dejong@arm.com } 1462810SN/A} 1472810SN/A 1482810SN/Avoid 1498856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1502810SN/A{ 1513013SN/A assert(blocked); 15210714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is accepting new requests\n"); 1533013SN/A blocked = false; 1548856Sandreas.hansson@arm.com if (mustSendRetry) { 15510714Sandreas.hansson@arm.com // @TODO: need to find a better time (next cycle?) 1568922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1572897SN/A } 1582810SN/A} 1592810SN/A 16010344Sandreas.hansson@arm.comvoid 16110344Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry() 16210344Sandreas.hansson@arm.com{ 16310714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is sending retry\n"); 16410344Sandreas.hansson@arm.com 16510344Sandreas.hansson@arm.com // reset the flag and call retry 16610344Sandreas.hansson@arm.com mustSendRetry = false; 16710713Sandreas.hansson@arm.com sendRetryReq(); 16810344Sandreas.hansson@arm.com} 1692844SN/A 17012730Sodanrc@yahoo.com.brAddr 17112730Sodanrc@yahoo.com.brBaseCache::regenerateBlkAddr(CacheBlk* blk) 17212730Sodanrc@yahoo.com.br{ 17312730Sodanrc@yahoo.com.br if (blk != tempBlock) { 17412730Sodanrc@yahoo.com.br return tags->regenerateBlkAddr(blk); 17512730Sodanrc@yahoo.com.br } else { 17612730Sodanrc@yahoo.com.br return tempBlock->getAddr(); 17712730Sodanrc@yahoo.com.br } 17812730Sodanrc@yahoo.com.br} 17912730Sodanrc@yahoo.com.br 1802810SN/Avoid 1812858SN/ABaseCache::init() 1822858SN/A{ 18312724Snikos.nikoleris@arm.com if (!cpuSidePort.isConnected() || !memSidePort.isConnected()) 1848922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 18512724Snikos.nikoleris@arm.com cpuSidePort.sendRangeChange(); 18612724Snikos.nikoleris@arm.com forwardSnoops = cpuSidePort.isSnooping(); 1872858SN/A} 1882858SN/A 18913784Sgabeblack@google.comPort & 19013784Sgabeblack@google.comBaseCache::getPort(const std::string &if_name, PortID idx) 1918922Swilliam.wang@arm.com{ 1928922Swilliam.wang@arm.com if (if_name == "mem_side") { 19312724Snikos.nikoleris@arm.com return memSidePort; 19413784Sgabeblack@google.com } else if (if_name == "cpu_side") { 19513784Sgabeblack@google.com return cpuSidePort; 1968922Swilliam.wang@arm.com } else { 19713892Sgabeblack@google.com return ClockedObject::getPort(if_name, idx); 1988922Swilliam.wang@arm.com } 1998922Swilliam.wang@arm.com} 2004628SN/A 20110821Sandreas.hansson@arm.combool 20210821Sandreas.hansson@arm.comBaseCache::inRange(Addr addr) const 20310821Sandreas.hansson@arm.com{ 20410821Sandreas.hansson@arm.com for (const auto& r : addrRanges) { 20510821Sandreas.hansson@arm.com if (r.contains(addr)) { 20610821Sandreas.hansson@arm.com return true; 20710821Sandreas.hansson@arm.com } 20810821Sandreas.hansson@arm.com } 20910821Sandreas.hansson@arm.com return false; 21010821Sandreas.hansson@arm.com} 21110821Sandreas.hansson@arm.com 2122858SN/Avoid 21312724Snikos.nikoleris@arm.comBaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) 21412724Snikos.nikoleris@arm.com{ 21512724Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 21613745Sodanrc@yahoo.com.br // These delays should have been consumed by now 21713745Sodanrc@yahoo.com.br assert(pkt->headerDelay == 0); 21813745Sodanrc@yahoo.com.br assert(pkt->payloadDelay == 0); 21913745Sodanrc@yahoo.com.br 22012724Snikos.nikoleris@arm.com pkt->makeTimingResponse(); 22112724Snikos.nikoleris@arm.com 22212724Snikos.nikoleris@arm.com // In this case we are considering request_time that takes 22312724Snikos.nikoleris@arm.com // into account the delay of the xbar, if any, and just 22412724Snikos.nikoleris@arm.com // lat, neglecting responseLatency, modelling hit latency 22513418Sodanrc@yahoo.com.br // just as the value of lat overriden by access(), which calls 22613418Sodanrc@yahoo.com.br // the calculateAccessLatency() function. 22713564Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(pkt, request_time); 22812724Snikos.nikoleris@arm.com } else { 22912724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 23012724Snikos.nikoleris@arm.com pkt->print()); 23112724Snikos.nikoleris@arm.com 23212724Snikos.nikoleris@arm.com // queue the packet for deletion, as the sending cache is 23312724Snikos.nikoleris@arm.com // still relying on it; if the block is found in access(), 23412724Snikos.nikoleris@arm.com // CleanEvict and Writeback messages will be deleted 23512724Snikos.nikoleris@arm.com // here as well 23612724Snikos.nikoleris@arm.com pendingDelete.reset(pkt); 23712724Snikos.nikoleris@arm.com } 23812724Snikos.nikoleris@arm.com} 23912724Snikos.nikoleris@arm.com 24012724Snikos.nikoleris@arm.comvoid 24112724Snikos.nikoleris@arm.comBaseCache::handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk, 24212724Snikos.nikoleris@arm.com Tick forward_time, Tick request_time) 24312724Snikos.nikoleris@arm.com{ 24413352Snikos.nikoleris@arm.com if (writeAllocator && 24513352Snikos.nikoleris@arm.com pkt && pkt->isWrite() && !pkt->req->isUncacheable()) { 24613352Snikos.nikoleris@arm.com writeAllocator->updateMode(pkt->getAddr(), pkt->getSize(), 24713352Snikos.nikoleris@arm.com pkt->getBlockAddr(blkSize)); 24813352Snikos.nikoleris@arm.com } 24913352Snikos.nikoleris@arm.com 25012724Snikos.nikoleris@arm.com if (mshr) { 25112724Snikos.nikoleris@arm.com /// MSHR hit 25212724Snikos.nikoleris@arm.com /// @note writebacks will be checked in getNextMSHR() 25312724Snikos.nikoleris@arm.com /// for any conflicting requests to the same block 25412724Snikos.nikoleris@arm.com 25512724Snikos.nikoleris@arm.com //@todo remove hw_pf here 25612724Snikos.nikoleris@arm.com 25712724Snikos.nikoleris@arm.com // Coalesce unless it was a software prefetch (see above). 25812724Snikos.nikoleris@arm.com if (pkt) { 25912724Snikos.nikoleris@arm.com assert(!pkt->isWriteback()); 26012724Snikos.nikoleris@arm.com // CleanEvicts corresponding to blocks which have 26112724Snikos.nikoleris@arm.com // outstanding requests in MSHRs are simply sunk here 26212724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 26312724Snikos.nikoleris@arm.com pendingDelete.reset(pkt); 26412724Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 26512724Snikos.nikoleris@arm.com // A WriteClean should never coalesce with any 26612724Snikos.nikoleris@arm.com // outstanding cache maintenance requests. 26712724Snikos.nikoleris@arm.com 26812724Snikos.nikoleris@arm.com // We use forward_time here because there is an 26912724Snikos.nikoleris@arm.com // uncached memory write, forwarded to WriteBuffer. 27012724Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 27112724Snikos.nikoleris@arm.com } else { 27212724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 27312724Snikos.nikoleris@arm.com pkt->print()); 27412724Snikos.nikoleris@arm.com 27512724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 27612724Snikos.nikoleris@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 27712724Snikos.nikoleris@arm.com 27812724Snikos.nikoleris@arm.com // We use forward_time here because it is the same 27912724Snikos.nikoleris@arm.com // considering new targets. We have multiple 28012724Snikos.nikoleris@arm.com // requests for the same address here. It 28112724Snikos.nikoleris@arm.com // specifies the latency to allocate an internal 28212724Snikos.nikoleris@arm.com // buffer and to schedule an event to the queued 28312724Snikos.nikoleris@arm.com // port and also takes into account the additional 28412724Snikos.nikoleris@arm.com // delay of the xbar. 28512724Snikos.nikoleris@arm.com mshr->allocateTarget(pkt, forward_time, order++, 28612724Snikos.nikoleris@arm.com allocOnFill(pkt->cmd)); 28712724Snikos.nikoleris@arm.com if (mshr->getNumTargets() == numTarget) { 28812724Snikos.nikoleris@arm.com noTargetMSHR = mshr; 28912724Snikos.nikoleris@arm.com setBlocked(Blocked_NoTargets); 29012724Snikos.nikoleris@arm.com // need to be careful with this... if this mshr isn't 29112724Snikos.nikoleris@arm.com // ready yet (i.e. time > curTick()), we don't want to 29212724Snikos.nikoleris@arm.com // move it ahead of mshrs that are ready 29312724Snikos.nikoleris@arm.com // mshrQueue.moveToFront(mshr); 29412724Snikos.nikoleris@arm.com } 29512724Snikos.nikoleris@arm.com } 29612724Snikos.nikoleris@arm.com } 29712724Snikos.nikoleris@arm.com } else { 29812724Snikos.nikoleris@arm.com // no MSHR 29912724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 30012724Snikos.nikoleris@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 30112724Snikos.nikoleris@arm.com 30212724Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) { 30312724Snikos.nikoleris@arm.com // We use forward_time here because there is an 30412724Snikos.nikoleris@arm.com // writeback or writeclean, forwarded to WriteBuffer. 30512724Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 30612724Snikos.nikoleris@arm.com } else { 30712724Snikos.nikoleris@arm.com if (blk && blk->isValid()) { 30812724Snikos.nikoleris@arm.com // If we have a write miss to a valid block, we 30912724Snikos.nikoleris@arm.com // need to mark the block non-readable. Otherwise 31012724Snikos.nikoleris@arm.com // if we allow reads while there's an outstanding 31112724Snikos.nikoleris@arm.com // write miss, the read could return stale data 31212724Snikos.nikoleris@arm.com // out of the cache block... a more aggressive 31312724Snikos.nikoleris@arm.com // system could detect the overlap (if any) and 31412724Snikos.nikoleris@arm.com // forward data out of the MSHRs, but we don't do 31512724Snikos.nikoleris@arm.com // that yet. Note that we do need to leave the 31612724Snikos.nikoleris@arm.com // block valid so that it stays in the cache, in 31712724Snikos.nikoleris@arm.com // case we get an upgrade response (and hence no 31812724Snikos.nikoleris@arm.com // new data) when the write miss completes. 31912724Snikos.nikoleris@arm.com // As long as CPUs do proper store/load forwarding 32012724Snikos.nikoleris@arm.com // internally, and have a sufficiently weak memory 32112724Snikos.nikoleris@arm.com // model, this is probably unnecessary, but at some 32212724Snikos.nikoleris@arm.com // point it must have seemed like we needed it... 32312724Snikos.nikoleris@arm.com assert((pkt->needsWritable() && !blk->isWritable()) || 32412724Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance()); 32512724Snikos.nikoleris@arm.com blk->status &= ~BlkReadable; 32612724Snikos.nikoleris@arm.com } 32712724Snikos.nikoleris@arm.com // Here we are using forward_time, modelling the latency of 32812724Snikos.nikoleris@arm.com // a miss (outbound) just as forwardLatency, neglecting the 32912724Snikos.nikoleris@arm.com // lookupLatency component. 33012724Snikos.nikoleris@arm.com allocateMissBuffer(pkt, forward_time); 33112724Snikos.nikoleris@arm.com } 33212724Snikos.nikoleris@arm.com } 33312724Snikos.nikoleris@arm.com} 33412724Snikos.nikoleris@arm.com 33512724Snikos.nikoleris@arm.comvoid 33612724Snikos.nikoleris@arm.comBaseCache::recvTimingReq(PacketPtr pkt) 33712724Snikos.nikoleris@arm.com{ 33812724Snikos.nikoleris@arm.com // anything that is merely forwarded pays for the forward latency and 33912724Snikos.nikoleris@arm.com // the delay provided by the crossbar 34012724Snikos.nikoleris@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 34112724Snikos.nikoleris@arm.com 34213418Sodanrc@yahoo.com.br Cycles lat; 34312724Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 34414035Sodanrc@yahoo.com.br bool satisfied = false; 34514035Sodanrc@yahoo.com.br { 34614035Sodanrc@yahoo.com.br PacketList writebacks; 34714035Sodanrc@yahoo.com.br // Note that lat is passed by reference here. The function 34814035Sodanrc@yahoo.com.br // access() will set the lat value. 34914035Sodanrc@yahoo.com.br satisfied = access(pkt, blk, lat, writebacks); 35014035Sodanrc@yahoo.com.br 35114035Sodanrc@yahoo.com.br // After the evicted blocks are selected, they must be forwarded 35214035Sodanrc@yahoo.com.br // to the write buffer to ensure they logically precede anything 35314035Sodanrc@yahoo.com.br // happening below 35414035Sodanrc@yahoo.com.br doWritebacks(writebacks, clockEdge(lat + forwardLatency)); 35514035Sodanrc@yahoo.com.br } 35612724Snikos.nikoleris@arm.com 35712724Snikos.nikoleris@arm.com // Here we charge the headerDelay that takes into account the latencies 35812724Snikos.nikoleris@arm.com // of the bus, if the packet comes from it. 35913418Sodanrc@yahoo.com.br // The latency charged is just the value set by the access() function. 36012724Snikos.nikoleris@arm.com // In case of a hit we are neglecting response latency. 36112724Snikos.nikoleris@arm.com // In case of a miss we are neglecting forward latency. 36213746Sodanrc@yahoo.com.br Tick request_time = clockEdge(lat); 36312724Snikos.nikoleris@arm.com // Here we reset the timing of the packet. 36412724Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 36512724Snikos.nikoleris@arm.com 36612724Snikos.nikoleris@arm.com if (satisfied) { 36713416Sjavier.bueno@metempsy.com // notify before anything else as later handleTimingReqHit might turn 36813416Sjavier.bueno@metempsy.com // the packet in a response 36913416Sjavier.bueno@metempsy.com ppHit->notify(pkt); 37012724Snikos.nikoleris@arm.com 37113416Sjavier.bueno@metempsy.com if (prefetcher && blk && blk->wasPrefetched()) { 37213416Sjavier.bueno@metempsy.com blk->status &= ~BlkHWPrefetched; 37312724Snikos.nikoleris@arm.com } 37412724Snikos.nikoleris@arm.com 37512724Snikos.nikoleris@arm.com handleTimingReqHit(pkt, blk, request_time); 37612724Snikos.nikoleris@arm.com } else { 37712724Snikos.nikoleris@arm.com handleTimingReqMiss(pkt, blk, forward_time, request_time); 37812724Snikos.nikoleris@arm.com 37913416Sjavier.bueno@metempsy.com ppMiss->notify(pkt); 38012724Snikos.nikoleris@arm.com } 38112724Snikos.nikoleris@arm.com 38213416Sjavier.bueno@metempsy.com if (prefetcher) { 38313416Sjavier.bueno@metempsy.com // track time of availability of next prefetch, if any 38413416Sjavier.bueno@metempsy.com Tick next_pf_time = prefetcher->nextPrefetchReadyTime(); 38513416Sjavier.bueno@metempsy.com if (next_pf_time != MaxTick) { 38613416Sjavier.bueno@metempsy.com schedMemSideSendEvent(next_pf_time); 38713416Sjavier.bueno@metempsy.com } 38812724Snikos.nikoleris@arm.com } 38912724Snikos.nikoleris@arm.com} 39012724Snikos.nikoleris@arm.com 39112724Snikos.nikoleris@arm.comvoid 39212724Snikos.nikoleris@arm.comBaseCache::handleUncacheableWriteResp(PacketPtr pkt) 39312724Snikos.nikoleris@arm.com{ 39412724Snikos.nikoleris@arm.com Tick completion_time = clockEdge(responseLatency) + 39512724Snikos.nikoleris@arm.com pkt->headerDelay + pkt->payloadDelay; 39612724Snikos.nikoleris@arm.com 39712724Snikos.nikoleris@arm.com // Reset the bus additional time as it is now accounted for 39812724Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 39912724Snikos.nikoleris@arm.com 40013564Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(pkt, completion_time); 40112724Snikos.nikoleris@arm.com} 40212724Snikos.nikoleris@arm.com 40312724Snikos.nikoleris@arm.comvoid 40412724Snikos.nikoleris@arm.comBaseCache::recvTimingResp(PacketPtr pkt) 40512724Snikos.nikoleris@arm.com{ 40612724Snikos.nikoleris@arm.com assert(pkt->isResponse()); 40712724Snikos.nikoleris@arm.com 40812724Snikos.nikoleris@arm.com // all header delay should be paid for by the crossbar, unless 40912724Snikos.nikoleris@arm.com // this is a prefetch response from above 41012724Snikos.nikoleris@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 41112724Snikos.nikoleris@arm.com "%s saw a non-zero packet delay\n", name()); 41212724Snikos.nikoleris@arm.com 41312724Snikos.nikoleris@arm.com const bool is_error = pkt->isError(); 41412724Snikos.nikoleris@arm.com 41512724Snikos.nikoleris@arm.com if (is_error) { 41612724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 41712724Snikos.nikoleris@arm.com pkt->print()); 41812724Snikos.nikoleris@arm.com } 41912724Snikos.nikoleris@arm.com 42012724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Handling response %s\n", __func__, 42112724Snikos.nikoleris@arm.com pkt->print()); 42212724Snikos.nikoleris@arm.com 42312724Snikos.nikoleris@arm.com // if this is a write, we should be looking at an uncacheable 42412724Snikos.nikoleris@arm.com // write 42512724Snikos.nikoleris@arm.com if (pkt->isWrite()) { 42612724Snikos.nikoleris@arm.com assert(pkt->req->isUncacheable()); 42712724Snikos.nikoleris@arm.com handleUncacheableWriteResp(pkt); 42812724Snikos.nikoleris@arm.com return; 42912724Snikos.nikoleris@arm.com } 43012724Snikos.nikoleris@arm.com 43112724Snikos.nikoleris@arm.com // we have dealt with any (uncacheable) writes above, from here on 43212724Snikos.nikoleris@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 43312724Snikos.nikoleris@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 43412724Snikos.nikoleris@arm.com assert(mshr); 43512724Snikos.nikoleris@arm.com 43612724Snikos.nikoleris@arm.com if (mshr == noTargetMSHR) { 43712724Snikos.nikoleris@arm.com // we always clear at least one target 43812724Snikos.nikoleris@arm.com clearBlocked(Blocked_NoTargets); 43912724Snikos.nikoleris@arm.com noTargetMSHR = nullptr; 44012724Snikos.nikoleris@arm.com } 44112724Snikos.nikoleris@arm.com 44212724Snikos.nikoleris@arm.com // Initial target is used just for stats 44313859Sodanrc@yahoo.com.br QueueEntry::Target *initial_tgt = mshr->getTarget(); 44412724Snikos.nikoleris@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 44512724Snikos.nikoleris@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 44612724Snikos.nikoleris@arm.com 44712724Snikos.nikoleris@arm.com if (pkt->req->isUncacheable()) { 44812724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 44912724Snikos.nikoleris@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 45012724Snikos.nikoleris@arm.com miss_latency; 45112724Snikos.nikoleris@arm.com } else { 45212724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 45312724Snikos.nikoleris@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 45412724Snikos.nikoleris@arm.com miss_latency; 45512724Snikos.nikoleris@arm.com } 45612724Snikos.nikoleris@arm.com 45714035Sodanrc@yahoo.com.br PacketList writebacks; 45814035Sodanrc@yahoo.com.br 45912724Snikos.nikoleris@arm.com bool is_fill = !mshr->isForward && 46013350Snikos.nikoleris@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp || 46113350Snikos.nikoleris@arm.com mshr->wasWholeLineWrite); 46213350Snikos.nikoleris@arm.com 46313350Snikos.nikoleris@arm.com // make sure that if the mshr was due to a whole line write then 46413350Snikos.nikoleris@arm.com // the response is an invalidation 46513350Snikos.nikoleris@arm.com assert(!mshr->wasWholeLineWrite || pkt->isInvalidate()); 46612724Snikos.nikoleris@arm.com 46712724Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 46812724Snikos.nikoleris@arm.com 46912724Snikos.nikoleris@arm.com if (is_fill && !is_error) { 47012724Snikos.nikoleris@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 47112724Snikos.nikoleris@arm.com pkt->getAddr()); 47212724Snikos.nikoleris@arm.com 47313352Snikos.nikoleris@arm.com const bool allocate = (writeAllocator && mshr->wasWholeLineWrite) ? 47413352Snikos.nikoleris@arm.com writeAllocator->allocate() : mshr->allocOnFill(); 47514035Sodanrc@yahoo.com.br blk = handleFill(pkt, blk, writebacks, allocate); 47612724Snikos.nikoleris@arm.com assert(blk != nullptr); 47713717Sivan.pizarro@metempsy.com ppFill->notify(pkt); 47812724Snikos.nikoleris@arm.com } 47912724Snikos.nikoleris@arm.com 48012724Snikos.nikoleris@arm.com if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) { 48112724Snikos.nikoleris@arm.com // The block was marked not readable while there was a pending 48212724Snikos.nikoleris@arm.com // cache maintenance operation, restore its flag. 48312724Snikos.nikoleris@arm.com blk->status |= BlkReadable; 48412794Snikos.nikoleris@arm.com 48512794Snikos.nikoleris@arm.com // This was a cache clean operation (without invalidate) 48612794Snikos.nikoleris@arm.com // and we have a copy of the block already. Since there 48712794Snikos.nikoleris@arm.com // is no invalidation, we can promote targets that don't 48812794Snikos.nikoleris@arm.com // require a writable copy 48912794Snikos.nikoleris@arm.com mshr->promoteReadable(); 49012724Snikos.nikoleris@arm.com } 49112724Snikos.nikoleris@arm.com 49212724Snikos.nikoleris@arm.com if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) { 49312724Snikos.nikoleris@arm.com // If at this point the referenced block is writable and the 49412724Snikos.nikoleris@arm.com // response is not a cache invalidate, we promote targets that 49512724Snikos.nikoleris@arm.com // were deferred as we couldn't guarrantee a writable copy 49612724Snikos.nikoleris@arm.com mshr->promoteWritable(); 49712724Snikos.nikoleris@arm.com } 49812724Snikos.nikoleris@arm.com 49913478Sodanrc@yahoo.com.br serviceMSHRTargets(mshr, pkt, blk); 50012724Snikos.nikoleris@arm.com 50112724Snikos.nikoleris@arm.com if (mshr->promoteDeferredTargets()) { 50212724Snikos.nikoleris@arm.com // avoid later read getting stale data while write miss is 50312724Snikos.nikoleris@arm.com // outstanding.. see comment in timingAccess() 50412724Snikos.nikoleris@arm.com if (blk) { 50512724Snikos.nikoleris@arm.com blk->status &= ~BlkReadable; 50612724Snikos.nikoleris@arm.com } 50712724Snikos.nikoleris@arm.com mshrQueue.markPending(mshr); 50812724Snikos.nikoleris@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 50912724Snikos.nikoleris@arm.com } else { 51012724Snikos.nikoleris@arm.com // while we deallocate an mshr from the queue we still have to 51112724Snikos.nikoleris@arm.com // check the isFull condition before and after as we might 51212724Snikos.nikoleris@arm.com // have been using the reserved entries already 51312724Snikos.nikoleris@arm.com const bool was_full = mshrQueue.isFull(); 51412724Snikos.nikoleris@arm.com mshrQueue.deallocate(mshr); 51512724Snikos.nikoleris@arm.com if (was_full && !mshrQueue.isFull()) { 51612724Snikos.nikoleris@arm.com clearBlocked(Blocked_NoMSHRs); 51712724Snikos.nikoleris@arm.com } 51812724Snikos.nikoleris@arm.com 51912724Snikos.nikoleris@arm.com // Request the bus for a prefetch if this deallocation freed enough 52012724Snikos.nikoleris@arm.com // MSHRs for a prefetch to take place 52112724Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 52212724Snikos.nikoleris@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 52312724Snikos.nikoleris@arm.com clockEdge()); 52412724Snikos.nikoleris@arm.com if (next_pf_time != MaxTick) 52512724Snikos.nikoleris@arm.com schedMemSideSendEvent(next_pf_time); 52612724Snikos.nikoleris@arm.com } 52712724Snikos.nikoleris@arm.com } 52812724Snikos.nikoleris@arm.com 52912724Snikos.nikoleris@arm.com // if we used temp block, check to see if its valid and then clear it out 53012724Snikos.nikoleris@arm.com if (blk == tempBlock && tempBlock->isValid()) { 53114035Sodanrc@yahoo.com.br evictBlock(blk, writebacks); 53212724Snikos.nikoleris@arm.com } 53312724Snikos.nikoleris@arm.com 53414035Sodanrc@yahoo.com.br const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 53514035Sodanrc@yahoo.com.br // copy writebacks to write buffer 53614035Sodanrc@yahoo.com.br doWritebacks(writebacks, forward_time); 53714035Sodanrc@yahoo.com.br 53812724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 53912724Snikos.nikoleris@arm.com delete pkt; 54012724Snikos.nikoleris@arm.com} 54112724Snikos.nikoleris@arm.com 54212724Snikos.nikoleris@arm.com 54312724Snikos.nikoleris@arm.comTick 54412724Snikos.nikoleris@arm.comBaseCache::recvAtomic(PacketPtr pkt) 54512724Snikos.nikoleris@arm.com{ 54612724Snikos.nikoleris@arm.com // should assert here that there are no outstanding MSHRs or 54712724Snikos.nikoleris@arm.com // writebacks... that would mean that someone used an atomic 54812724Snikos.nikoleris@arm.com // access in timing mode 54912724Snikos.nikoleris@arm.com 55013412Snikos.nikoleris@arm.com // We use lookupLatency here because it is used to specify the latency 55113412Snikos.nikoleris@arm.com // to access. 55213412Snikos.nikoleris@arm.com Cycles lat = lookupLatency; 55313412Snikos.nikoleris@arm.com 55412724Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 55514035Sodanrc@yahoo.com.br PacketList writebacks; 55614035Sodanrc@yahoo.com.br bool satisfied = access(pkt, blk, lat, writebacks); 55712724Snikos.nikoleris@arm.com 55812724Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 55912724Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 56012724Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 56112724Snikos.nikoleris@arm.com // will update any copies to the path to the memory 56212724Snikos.nikoleris@arm.com // until the point of reference. 56312724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 56412724Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 56512724Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 56614035Sodanrc@yahoo.com.br writebacks.push_back(wb_pkt); 56712724Snikos.nikoleris@arm.com pkt->setSatisfied(); 56812724Snikos.nikoleris@arm.com } 56912724Snikos.nikoleris@arm.com 57014035Sodanrc@yahoo.com.br // handle writebacks resulting from the access here to ensure they 57114035Sodanrc@yahoo.com.br // logically precede anything happening below 57214035Sodanrc@yahoo.com.br doWritebacksAtomic(writebacks); 57314035Sodanrc@yahoo.com.br assert(writebacks.empty()); 57414035Sodanrc@yahoo.com.br 57512724Snikos.nikoleris@arm.com if (!satisfied) { 57614035Sodanrc@yahoo.com.br lat += handleAtomicReqMiss(pkt, blk, writebacks); 57712724Snikos.nikoleris@arm.com } 57812724Snikos.nikoleris@arm.com 57912724Snikos.nikoleris@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 58012724Snikos.nikoleris@arm.com // It's not clear how to do it properly, particularly for 58112724Snikos.nikoleris@arm.com // prefetchers that aggressively generate prefetch candidates and 58212724Snikos.nikoleris@arm.com // rely on bandwidth contention to throttle them; these will tend 58312724Snikos.nikoleris@arm.com // to pollute the cache in atomic mode since there is no bandwidth 58412724Snikos.nikoleris@arm.com // contention. If we ever do want to enable prefetching in atomic 58512724Snikos.nikoleris@arm.com // mode, though, this is the place to do it... see timingAccess() 58612724Snikos.nikoleris@arm.com // for an example (though we'd want to issue the prefetch(es) 58712724Snikos.nikoleris@arm.com // immediately rather than calling requestMemSideBus() as we do 58812724Snikos.nikoleris@arm.com // there). 58912724Snikos.nikoleris@arm.com 59014035Sodanrc@yahoo.com.br // do any writebacks resulting from the response handling 59114035Sodanrc@yahoo.com.br doWritebacksAtomic(writebacks); 59214035Sodanrc@yahoo.com.br 59312724Snikos.nikoleris@arm.com // if we used temp block, check to see if its valid and if so 59412724Snikos.nikoleris@arm.com // clear it out, but only do so after the call to recvAtomic is 59512724Snikos.nikoleris@arm.com // finished so that any downstream observers (such as a snoop 59612724Snikos.nikoleris@arm.com // filter), first see the fill, and only then see the eviction 59712724Snikos.nikoleris@arm.com if (blk == tempBlock && tempBlock->isValid()) { 59812724Snikos.nikoleris@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 59912724Snikos.nikoleris@arm.com // sequentuially, and we may already have a tempBlock 60012724Snikos.nikoleris@arm.com // writeback from the fetch that we have not yet sent 60112724Snikos.nikoleris@arm.com if (tempBlockWriteback) { 60212724Snikos.nikoleris@arm.com // if that is the case, write the prevoius one back, and 60312724Snikos.nikoleris@arm.com // do not schedule any new event 60412724Snikos.nikoleris@arm.com writebackTempBlockAtomic(); 60512724Snikos.nikoleris@arm.com } else { 60612724Snikos.nikoleris@arm.com // the writeback/clean eviction happens after the call to 60712724Snikos.nikoleris@arm.com // recvAtomic has finished (but before any successive 60812724Snikos.nikoleris@arm.com // calls), so that the response handling from the fill is 60912724Snikos.nikoleris@arm.com // allowed to happen first 61012724Snikos.nikoleris@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 61112724Snikos.nikoleris@arm.com } 61212724Snikos.nikoleris@arm.com 61312724Snikos.nikoleris@arm.com tempBlockWriteback = evictBlock(blk); 61412724Snikos.nikoleris@arm.com } 61512724Snikos.nikoleris@arm.com 61612724Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 61712724Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 61812724Snikos.nikoleris@arm.com } 61912724Snikos.nikoleris@arm.com 62012724Snikos.nikoleris@arm.com return lat * clockPeriod(); 62112724Snikos.nikoleris@arm.com} 62212724Snikos.nikoleris@arm.com 62312724Snikos.nikoleris@arm.comvoid 62412724Snikos.nikoleris@arm.comBaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side) 62512724Snikos.nikoleris@arm.com{ 62612724Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 62712724Snikos.nikoleris@arm.com bool is_secure = pkt->isSecure(); 62812724Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 62912724Snikos.nikoleris@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 63012724Snikos.nikoleris@arm.com 63112724Snikos.nikoleris@arm.com pkt->pushLabel(name()); 63212724Snikos.nikoleris@arm.com 63312724Snikos.nikoleris@arm.com CacheBlkPrintWrapper cbpw(blk); 63412724Snikos.nikoleris@arm.com 63512724Snikos.nikoleris@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 63612724Snikos.nikoleris@arm.com // L1 doesn't have a more up-to-date modified copy that still 63712724Snikos.nikoleris@arm.com // needs to be found. As a result we always update the request if 63812724Snikos.nikoleris@arm.com // we have it, but only declare it satisfied if we are the owner. 63912724Snikos.nikoleris@arm.com 64012724Snikos.nikoleris@arm.com // see if we have data at all (owned or otherwise) 64112724Snikos.nikoleris@arm.com bool have_data = blk && blk->isValid() 64212823Srmk35@cl.cam.ac.uk && pkt->trySatisfyFunctional(&cbpw, blk_addr, is_secure, blkSize, 64312823Srmk35@cl.cam.ac.uk blk->data); 64412724Snikos.nikoleris@arm.com 64512724Snikos.nikoleris@arm.com // data we have is dirty if marked as such or if we have an 64612724Snikos.nikoleris@arm.com // in-service MSHR that is pending a modified line 64712724Snikos.nikoleris@arm.com bool have_dirty = 64812724Snikos.nikoleris@arm.com have_data && (blk->isDirty() || 64912724Snikos.nikoleris@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 65012724Snikos.nikoleris@arm.com 65112724Snikos.nikoleris@arm.com bool done = have_dirty || 65212823Srmk35@cl.cam.ac.uk cpuSidePort.trySatisfyFunctional(pkt) || 65313862Sodanrc@yahoo.com.br mshrQueue.trySatisfyFunctional(pkt) || 65413862Sodanrc@yahoo.com.br writeBuffer.trySatisfyFunctional(pkt) || 65512823Srmk35@cl.cam.ac.uk memSidePort.trySatisfyFunctional(pkt); 65612724Snikos.nikoleris@arm.com 65712724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 65812724Snikos.nikoleris@arm.com (blk && blk->isValid()) ? "valid " : "", 65912724Snikos.nikoleris@arm.com have_data ? "data " : "", done ? "done " : ""); 66012724Snikos.nikoleris@arm.com 66112724Snikos.nikoleris@arm.com // We're leaving the cache, so pop cache->name() label 66212724Snikos.nikoleris@arm.com pkt->popLabel(); 66312724Snikos.nikoleris@arm.com 66412724Snikos.nikoleris@arm.com if (done) { 66512724Snikos.nikoleris@arm.com pkt->makeResponse(); 66612724Snikos.nikoleris@arm.com } else { 66712724Snikos.nikoleris@arm.com // if it came as a request from the CPU side then make sure it 66812724Snikos.nikoleris@arm.com // continues towards the memory side 66912724Snikos.nikoleris@arm.com if (from_cpu_side) { 67012724Snikos.nikoleris@arm.com memSidePort.sendFunctional(pkt); 67112724Snikos.nikoleris@arm.com } else if (cpuSidePort.isSnooping()) { 67212724Snikos.nikoleris@arm.com // if it came from the memory side, it must be a snoop request 67312724Snikos.nikoleris@arm.com // and we should only forward it if we are forwarding snoops 67412724Snikos.nikoleris@arm.com cpuSidePort.sendFunctionalSnoop(pkt); 67512724Snikos.nikoleris@arm.com } 67612724Snikos.nikoleris@arm.com } 67712724Snikos.nikoleris@arm.com} 67812724Snikos.nikoleris@arm.com 67912724Snikos.nikoleris@arm.com 68012724Snikos.nikoleris@arm.comvoid 68112724Snikos.nikoleris@arm.comBaseCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 68212724Snikos.nikoleris@arm.com{ 68312724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 68412724Snikos.nikoleris@arm.com 68512724Snikos.nikoleris@arm.com uint64_t overwrite_val; 68612724Snikos.nikoleris@arm.com bool overwrite_mem; 68712724Snikos.nikoleris@arm.com uint64_t condition_val64; 68812724Snikos.nikoleris@arm.com uint32_t condition_val32; 68912724Snikos.nikoleris@arm.com 69012724Snikos.nikoleris@arm.com int offset = pkt->getOffset(blkSize); 69112724Snikos.nikoleris@arm.com uint8_t *blk_data = blk->data + offset; 69212724Snikos.nikoleris@arm.com 69312724Snikos.nikoleris@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 69412724Snikos.nikoleris@arm.com 69512724Snikos.nikoleris@arm.com overwrite_mem = true; 69612724Snikos.nikoleris@arm.com // keep a copy of our possible write value, and copy what is at the 69712724Snikos.nikoleris@arm.com // memory address into the packet 69812724Snikos.nikoleris@arm.com pkt->writeData((uint8_t *)&overwrite_val); 69912724Snikos.nikoleris@arm.com pkt->setData(blk_data); 70012724Snikos.nikoleris@arm.com 70112724Snikos.nikoleris@arm.com if (pkt->req->isCondSwap()) { 70212724Snikos.nikoleris@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 70312724Snikos.nikoleris@arm.com condition_val64 = pkt->req->getExtraData(); 70412724Snikos.nikoleris@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 70512724Snikos.nikoleris@arm.com sizeof(uint64_t)); 70612724Snikos.nikoleris@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 70712724Snikos.nikoleris@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 70812724Snikos.nikoleris@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 70912724Snikos.nikoleris@arm.com sizeof(uint32_t)); 71012724Snikos.nikoleris@arm.com } else 71112724Snikos.nikoleris@arm.com panic("Invalid size for conditional read/write\n"); 71212724Snikos.nikoleris@arm.com } 71312724Snikos.nikoleris@arm.com 71412724Snikos.nikoleris@arm.com if (overwrite_mem) { 71512724Snikos.nikoleris@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 71612724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 71712724Snikos.nikoleris@arm.com } 71812724Snikos.nikoleris@arm.com} 71912724Snikos.nikoleris@arm.com 72012724Snikos.nikoleris@arm.comQueueEntry* 72112724Snikos.nikoleris@arm.comBaseCache::getNextQueueEntry() 72212724Snikos.nikoleris@arm.com{ 72312724Snikos.nikoleris@arm.com // Check both MSHR queue and write buffer for potential requests, 72412724Snikos.nikoleris@arm.com // note that null does not mean there is no request, it could 72512724Snikos.nikoleris@arm.com // simply be that it is not ready 72612724Snikos.nikoleris@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 72712724Snikos.nikoleris@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 72812724Snikos.nikoleris@arm.com 72912724Snikos.nikoleris@arm.com // If we got a write buffer request ready, first priority is a 73012724Snikos.nikoleris@arm.com // full write buffer, otherwise we favour the miss requests 73112724Snikos.nikoleris@arm.com if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 73212724Snikos.nikoleris@arm.com // need to search MSHR queue for conflicting earlier miss. 73313861Sodanrc@yahoo.com.br MSHR *conflict_mshr = mshrQueue.findPending(wq_entry); 73412724Snikos.nikoleris@arm.com 73512724Snikos.nikoleris@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 73612724Snikos.nikoleris@arm.com // Service misses in order until conflict is cleared. 73712724Snikos.nikoleris@arm.com return conflict_mshr; 73812724Snikos.nikoleris@arm.com 73912724Snikos.nikoleris@arm.com // @todo Note that we ignore the ready time of the conflict here 74012724Snikos.nikoleris@arm.com } 74112724Snikos.nikoleris@arm.com 74212724Snikos.nikoleris@arm.com // No conflicts; issue write 74312724Snikos.nikoleris@arm.com return wq_entry; 74412724Snikos.nikoleris@arm.com } else if (miss_mshr) { 74512724Snikos.nikoleris@arm.com // need to check for conflicting earlier writeback 74613861Sodanrc@yahoo.com.br WriteQueueEntry *conflict_mshr = writeBuffer.findPending(miss_mshr); 74712724Snikos.nikoleris@arm.com if (conflict_mshr) { 74812724Snikos.nikoleris@arm.com // not sure why we don't check order here... it was in the 74912724Snikos.nikoleris@arm.com // original code but commented out. 75012724Snikos.nikoleris@arm.com 75112724Snikos.nikoleris@arm.com // The only way this happens is if we are 75212724Snikos.nikoleris@arm.com // doing a write and we didn't have permissions 75312724Snikos.nikoleris@arm.com // then subsequently saw a writeback (owned got evicted) 75412724Snikos.nikoleris@arm.com // We need to make sure to perform the writeback first 75512724Snikos.nikoleris@arm.com // To preserve the dirty data, then we can issue the write 75612724Snikos.nikoleris@arm.com 75712724Snikos.nikoleris@arm.com // should we return wq_entry here instead? I.e. do we 75812724Snikos.nikoleris@arm.com // have to flush writes in order? I don't think so... not 75912724Snikos.nikoleris@arm.com // for Alpha anyway. Maybe for x86? 76012724Snikos.nikoleris@arm.com return conflict_mshr; 76112724Snikos.nikoleris@arm.com 76212724Snikos.nikoleris@arm.com // @todo Note that we ignore the ready time of the conflict here 76312724Snikos.nikoleris@arm.com } 76412724Snikos.nikoleris@arm.com 76512724Snikos.nikoleris@arm.com // No conflicts; issue read 76612724Snikos.nikoleris@arm.com return miss_mshr; 76712724Snikos.nikoleris@arm.com } 76812724Snikos.nikoleris@arm.com 76912724Snikos.nikoleris@arm.com // fall through... no pending requests. Try a prefetch. 77012724Snikos.nikoleris@arm.com assert(!miss_mshr && !wq_entry); 77112724Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 77212724Snikos.nikoleris@arm.com // If we have a miss queue slot, we can try a prefetch 77312724Snikos.nikoleris@arm.com PacketPtr pkt = prefetcher->getPacket(); 77412724Snikos.nikoleris@arm.com if (pkt) { 77512724Snikos.nikoleris@arm.com Addr pf_addr = pkt->getBlockAddr(blkSize); 77612724Snikos.nikoleris@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 77712724Snikos.nikoleris@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 77812724Snikos.nikoleris@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 77912724Snikos.nikoleris@arm.com // Update statistic on number of prefetches issued 78012724Snikos.nikoleris@arm.com // (hwpf_mshr_misses) 78112724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 78212724Snikos.nikoleris@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 78312724Snikos.nikoleris@arm.com 78412724Snikos.nikoleris@arm.com // allocate an MSHR and return it, note 78512724Snikos.nikoleris@arm.com // that we send the packet straight away, so do not 78612724Snikos.nikoleris@arm.com // schedule the send 78712724Snikos.nikoleris@arm.com return allocateMissBuffer(pkt, curTick(), false); 78812724Snikos.nikoleris@arm.com } else { 78912724Snikos.nikoleris@arm.com // free the request and packet 79012724Snikos.nikoleris@arm.com delete pkt; 79112724Snikos.nikoleris@arm.com } 79212724Snikos.nikoleris@arm.com } 79312724Snikos.nikoleris@arm.com } 79412724Snikos.nikoleris@arm.com 79512724Snikos.nikoleris@arm.com return nullptr; 79612724Snikos.nikoleris@arm.com} 79712724Snikos.nikoleris@arm.com 79813947Sodanrc@yahoo.com.brbool 79913947Sodanrc@yahoo.com.brBaseCache::updateCompressionData(CacheBlk *blk, const uint64_t* data, 80014035Sodanrc@yahoo.com.br PacketList &writebacks) 80113947Sodanrc@yahoo.com.br{ 80213947Sodanrc@yahoo.com.br // tempBlock does not exist in the tags, so don't do anything for it. 80313947Sodanrc@yahoo.com.br if (blk == tempBlock) { 80413947Sodanrc@yahoo.com.br return true; 80513947Sodanrc@yahoo.com.br } 80613947Sodanrc@yahoo.com.br 80713947Sodanrc@yahoo.com.br // Get superblock of the given block 80813947Sodanrc@yahoo.com.br CompressionBlk* compression_blk = static_cast<CompressionBlk*>(blk); 80913947Sodanrc@yahoo.com.br const SuperBlk* superblock = static_cast<const SuperBlk*>( 81013947Sodanrc@yahoo.com.br compression_blk->getSectorBlock()); 81113947Sodanrc@yahoo.com.br 81213947Sodanrc@yahoo.com.br // The compressor is called to compress the updated data, so that its 81313947Sodanrc@yahoo.com.br // metadata can be updated. 81413947Sodanrc@yahoo.com.br std::size_t compression_size = 0; 81513947Sodanrc@yahoo.com.br Cycles compression_lat = Cycles(0); 81613947Sodanrc@yahoo.com.br Cycles decompression_lat = Cycles(0); 81713947Sodanrc@yahoo.com.br compressor->compress(data, compression_lat, decompression_lat, 81813947Sodanrc@yahoo.com.br compression_size); 81913947Sodanrc@yahoo.com.br 82013947Sodanrc@yahoo.com.br // If block's compression factor increased, it may not be co-allocatable 82113947Sodanrc@yahoo.com.br // anymore. If so, some blocks might need to be evicted to make room for 82213947Sodanrc@yahoo.com.br // the bigger block 82313947Sodanrc@yahoo.com.br 82413947Sodanrc@yahoo.com.br // Get previous compressed size 82513947Sodanrc@yahoo.com.br const std::size_t M5_VAR_USED prev_size = compression_blk->getSizeBits(); 82613947Sodanrc@yahoo.com.br 82713947Sodanrc@yahoo.com.br // Check if new data is co-allocatable 82813947Sodanrc@yahoo.com.br const bool is_co_allocatable = superblock->isCompressed(compression_blk) && 82913947Sodanrc@yahoo.com.br superblock->canCoAllocate(compression_size); 83013947Sodanrc@yahoo.com.br 83113947Sodanrc@yahoo.com.br // If block was compressed, possibly co-allocated with other blocks, and 83213947Sodanrc@yahoo.com.br // cannot be co-allocated anymore, one or more blocks must be evicted to 83313947Sodanrc@yahoo.com.br // make room for the expanded block. As of now we decide to evict the co- 83413947Sodanrc@yahoo.com.br // allocated blocks to make room for the expansion, but other approaches 83513947Sodanrc@yahoo.com.br // that take the replacement data of the superblock into account may 83613947Sodanrc@yahoo.com.br // generate better results 83713947Sodanrc@yahoo.com.br std::vector<CacheBlk*> evict_blks; 83813947Sodanrc@yahoo.com.br const bool was_compressed = compression_blk->isCompressed(); 83913947Sodanrc@yahoo.com.br if (was_compressed && !is_co_allocatable) { 84013947Sodanrc@yahoo.com.br // Get all co-allocated blocks 84113947Sodanrc@yahoo.com.br for (const auto& sub_blk : superblock->blks) { 84213947Sodanrc@yahoo.com.br if (sub_blk->isValid() && (compression_blk != sub_blk)) { 84313947Sodanrc@yahoo.com.br // Check for transient state allocations. If any of the 84413947Sodanrc@yahoo.com.br // entries listed for eviction has a transient state, the 84513947Sodanrc@yahoo.com.br // allocation fails 84613947Sodanrc@yahoo.com.br const Addr repl_addr = regenerateBlkAddr(sub_blk); 84713947Sodanrc@yahoo.com.br const MSHR *repl_mshr = 84813947Sodanrc@yahoo.com.br mshrQueue.findMatch(repl_addr, sub_blk->isSecure()); 84913947Sodanrc@yahoo.com.br if (repl_mshr) { 85013947Sodanrc@yahoo.com.br DPRINTF(CacheRepl, "Aborting data expansion of %s due " \ 85113947Sodanrc@yahoo.com.br "to replacement of block in transient state: %s\n", 85213947Sodanrc@yahoo.com.br compression_blk->print(), sub_blk->print()); 85313947Sodanrc@yahoo.com.br // Too hard to replace block with transient state, so it 85413947Sodanrc@yahoo.com.br // cannot be evicted. Mark the update as failed and expect 85513947Sodanrc@yahoo.com.br // the caller to evict this block. Since this is called 85613947Sodanrc@yahoo.com.br // only when writebacks arrive, and packets do not contain 85713947Sodanrc@yahoo.com.br // compressed data, there is no need to decompress 85813947Sodanrc@yahoo.com.br compression_blk->setSizeBits(blkSize * 8); 85913947Sodanrc@yahoo.com.br compression_blk->setDecompressionLatency(Cycles(0)); 86013947Sodanrc@yahoo.com.br compression_blk->setUncompressed(); 86113947Sodanrc@yahoo.com.br return false; 86213947Sodanrc@yahoo.com.br } 86313947Sodanrc@yahoo.com.br 86413947Sodanrc@yahoo.com.br evict_blks.push_back(sub_blk); 86513947Sodanrc@yahoo.com.br } 86613947Sodanrc@yahoo.com.br } 86713947Sodanrc@yahoo.com.br 86813947Sodanrc@yahoo.com.br // Update the number of data expansions 86913947Sodanrc@yahoo.com.br dataExpansions++; 87013947Sodanrc@yahoo.com.br 87113947Sodanrc@yahoo.com.br DPRINTF(CacheComp, "Data expansion: expanding [%s] from %d to %d bits" 87213947Sodanrc@yahoo.com.br "\n", blk->print(), prev_size, compression_size); 87313947Sodanrc@yahoo.com.br } 87413947Sodanrc@yahoo.com.br 87513947Sodanrc@yahoo.com.br // We always store compressed blocks when possible 87613947Sodanrc@yahoo.com.br if (is_co_allocatable) { 87713947Sodanrc@yahoo.com.br compression_blk->setCompressed(); 87813947Sodanrc@yahoo.com.br } else { 87913947Sodanrc@yahoo.com.br compression_blk->setUncompressed(); 88013947Sodanrc@yahoo.com.br } 88113947Sodanrc@yahoo.com.br compression_blk->setSizeBits(compression_size); 88213947Sodanrc@yahoo.com.br compression_blk->setDecompressionLatency(decompression_lat); 88313947Sodanrc@yahoo.com.br 88413947Sodanrc@yahoo.com.br // Evict valid blocks 88513947Sodanrc@yahoo.com.br for (const auto& evict_blk : evict_blks) { 88613947Sodanrc@yahoo.com.br if (evict_blk->isValid()) { 88713947Sodanrc@yahoo.com.br if (evict_blk->wasPrefetched()) { 88813947Sodanrc@yahoo.com.br unusedPrefetches++; 88913947Sodanrc@yahoo.com.br } 89014035Sodanrc@yahoo.com.br evictBlock(evict_blk, writebacks); 89113947Sodanrc@yahoo.com.br } 89213947Sodanrc@yahoo.com.br } 89313947Sodanrc@yahoo.com.br 89413947Sodanrc@yahoo.com.br return true; 89513947Sodanrc@yahoo.com.br} 89613947Sodanrc@yahoo.com.br 89712724Snikos.nikoleris@arm.comvoid 89812724Snikos.nikoleris@arm.comBaseCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool) 89912724Snikos.nikoleris@arm.com{ 90012724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 90112724Snikos.nikoleris@arm.com 90212724Snikos.nikoleris@arm.com assert(blk && blk->isValid()); 90312724Snikos.nikoleris@arm.com // Occasionally this is not true... if we are a lower-level cache 90412724Snikos.nikoleris@arm.com // satisfying a string of Read and ReadEx requests from 90512724Snikos.nikoleris@arm.com // upper-level caches, a Read will mark the block as shared but we 90612724Snikos.nikoleris@arm.com // can satisfy a following ReadEx anyway since we can rely on the 90712724Snikos.nikoleris@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 90812724Snikos.nikoleris@arm.com // invalidate their blocks after receiving them. 90912724Snikos.nikoleris@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 91012724Snikos.nikoleris@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 91112724Snikos.nikoleris@arm.com 91212724Snikos.nikoleris@arm.com // Check RMW operations first since both isRead() and 91312724Snikos.nikoleris@arm.com // isWrite() will be true for them 91412724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::SwapReq) { 91512766Sqtt2@cornell.edu if (pkt->isAtomicOp()) { 91612766Sqtt2@cornell.edu // extract data from cache and save it into the data field in 91712766Sqtt2@cornell.edu // the packet as a return value from this atomic op 91812766Sqtt2@cornell.edu int offset = tags->extractBlkOffset(pkt->getAddr()); 91912766Sqtt2@cornell.edu uint8_t *blk_data = blk->data + offset; 92013377Sodanrc@yahoo.com.br pkt->setData(blk_data); 92112766Sqtt2@cornell.edu 92212766Sqtt2@cornell.edu // execute AMO operation 92312766Sqtt2@cornell.edu (*(pkt->getAtomicOp()))(blk_data); 92412766Sqtt2@cornell.edu 92512766Sqtt2@cornell.edu // set block status to dirty 92612766Sqtt2@cornell.edu blk->status |= BlkDirty; 92712766Sqtt2@cornell.edu } else { 92812766Sqtt2@cornell.edu cmpAndSwap(blk, pkt); 92912766Sqtt2@cornell.edu } 93012724Snikos.nikoleris@arm.com } else if (pkt->isWrite()) { 93112724Snikos.nikoleris@arm.com // we have the block in a writable state and can go ahead, 93212724Snikos.nikoleris@arm.com // note that the line may be also be considered writable in 93312724Snikos.nikoleris@arm.com // downstream caches along the path to memory, but always 93412724Snikos.nikoleris@arm.com // Exclusive, and never Modified 93512724Snikos.nikoleris@arm.com assert(blk->isWritable()); 93612724Snikos.nikoleris@arm.com // Write or WriteLine at the first cache with block in writable state 93712724Snikos.nikoleris@arm.com if (blk->checkWrite(pkt)) { 93812724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 93912724Snikos.nikoleris@arm.com } 94012724Snikos.nikoleris@arm.com // Always mark the line as dirty (and thus transition to the 94112724Snikos.nikoleris@arm.com // Modified state) even if we are a failed StoreCond so we 94212724Snikos.nikoleris@arm.com // supply data to any snoops that have appended themselves to 94312724Snikos.nikoleris@arm.com // this cache before knowing the store will fail. 94412724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 94512724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 94612724Snikos.nikoleris@arm.com } else if (pkt->isRead()) { 94712724Snikos.nikoleris@arm.com if (pkt->isLLSC()) { 94812724Snikos.nikoleris@arm.com blk->trackLoadLocked(pkt); 94912724Snikos.nikoleris@arm.com } 95012724Snikos.nikoleris@arm.com 95112724Snikos.nikoleris@arm.com // all read responses have a data payload 95212724Snikos.nikoleris@arm.com assert(pkt->hasRespData()); 95312724Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 95412724Snikos.nikoleris@arm.com } else if (pkt->isUpgrade()) { 95512724Snikos.nikoleris@arm.com // sanity check 95612724Snikos.nikoleris@arm.com assert(!pkt->hasSharers()); 95712724Snikos.nikoleris@arm.com 95812724Snikos.nikoleris@arm.com if (blk->isDirty()) { 95912724Snikos.nikoleris@arm.com // we were in the Owned state, and a cache above us that 96012724Snikos.nikoleris@arm.com // has the line in Shared state needs to be made aware 96112724Snikos.nikoleris@arm.com // that the data it already has is in fact dirty 96212724Snikos.nikoleris@arm.com pkt->setCacheResponding(); 96312724Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 96412724Snikos.nikoleris@arm.com } 96512794Snikos.nikoleris@arm.com } else if (pkt->isClean()) { 96612794Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 96712724Snikos.nikoleris@arm.com } else { 96812724Snikos.nikoleris@arm.com assert(pkt->isInvalidate()); 96912724Snikos.nikoleris@arm.com invalidateBlock(blk); 97012724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 97112724Snikos.nikoleris@arm.com pkt->print()); 97212724Snikos.nikoleris@arm.com } 97312724Snikos.nikoleris@arm.com} 97412724Snikos.nikoleris@arm.com 97512724Snikos.nikoleris@arm.com///////////////////////////////////////////////////// 97612724Snikos.nikoleris@arm.com// 97712724Snikos.nikoleris@arm.com// Access path: requests coming in from the CPU side 97812724Snikos.nikoleris@arm.com// 97912724Snikos.nikoleris@arm.com///////////////////////////////////////////////////// 98013418Sodanrc@yahoo.com.brCycles 98113749Sodanrc@yahoo.com.brBaseCache::calculateTagOnlyLatency(const uint32_t delay, 98213749Sodanrc@yahoo.com.br const Cycles lookup_lat) const 98313749Sodanrc@yahoo.com.br{ 98413749Sodanrc@yahoo.com.br // A tag-only access has to wait for the packet to arrive in order to 98513749Sodanrc@yahoo.com.br // perform the tag lookup. 98613749Sodanrc@yahoo.com.br return ticksToCycles(delay) + lookup_lat; 98713749Sodanrc@yahoo.com.br} 98813749Sodanrc@yahoo.com.br 98913749Sodanrc@yahoo.com.brCycles 99013746Sodanrc@yahoo.com.brBaseCache::calculateAccessLatency(const CacheBlk* blk, const uint32_t delay, 99113418Sodanrc@yahoo.com.br const Cycles lookup_lat) const 99213418Sodanrc@yahoo.com.br{ 99313746Sodanrc@yahoo.com.br Cycles lat(0); 99413418Sodanrc@yahoo.com.br 99513418Sodanrc@yahoo.com.br if (blk != nullptr) { 99613746Sodanrc@yahoo.com.br // As soon as the access arrives, for sequential accesses first access 99713746Sodanrc@yahoo.com.br // tags, then the data entry. In the case of parallel accesses the 99813746Sodanrc@yahoo.com.br // latency is dictated by the slowest of tag and data latencies. 99913418Sodanrc@yahoo.com.br if (sequentialAccess) { 100013746Sodanrc@yahoo.com.br lat = ticksToCycles(delay) + lookup_lat + dataLatency; 100113418Sodanrc@yahoo.com.br } else { 100213746Sodanrc@yahoo.com.br lat = ticksToCycles(delay) + std::max(lookup_lat, dataLatency); 100313418Sodanrc@yahoo.com.br } 100413418Sodanrc@yahoo.com.br 100513418Sodanrc@yahoo.com.br // Check if the block to be accessed is available. If not, apply the 100613477Sodanrc@yahoo.com.br // access latency on top of when the block is ready to be accessed. 100713746Sodanrc@yahoo.com.br const Tick tick = curTick() + delay; 100813477Sodanrc@yahoo.com.br const Tick when_ready = blk->getWhenReady(); 100913746Sodanrc@yahoo.com.br if (when_ready > tick && 101013746Sodanrc@yahoo.com.br ticksToCycles(when_ready - tick) > lat) { 101113746Sodanrc@yahoo.com.br lat += ticksToCycles(when_ready - tick); 101213418Sodanrc@yahoo.com.br } 101313746Sodanrc@yahoo.com.br } else { 101413749Sodanrc@yahoo.com.br // In case of a miss, we neglect the data access in a parallel 101513749Sodanrc@yahoo.com.br // configuration (i.e., the data access will be stopped as soon as 101613749Sodanrc@yahoo.com.br // we find out it is a miss), and use the tag-only latency. 101713749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(delay, lookup_lat); 101813418Sodanrc@yahoo.com.br } 101913418Sodanrc@yahoo.com.br 102013418Sodanrc@yahoo.com.br return lat; 102113418Sodanrc@yahoo.com.br} 102212724Snikos.nikoleris@arm.com 102312724Snikos.nikoleris@arm.combool 102414035Sodanrc@yahoo.com.brBaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 102514035Sodanrc@yahoo.com.br PacketList &writebacks) 102612724Snikos.nikoleris@arm.com{ 102712724Snikos.nikoleris@arm.com // sanity check 102812724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 102912724Snikos.nikoleris@arm.com 103012724Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 103112724Snikos.nikoleris@arm.com "Should never see a write in a read-only cache %s\n", 103212724Snikos.nikoleris@arm.com name()); 103312724Snikos.nikoleris@arm.com 103413418Sodanrc@yahoo.com.br // Access block in the tags 103513418Sodanrc@yahoo.com.br Cycles tag_latency(0); 103613418Sodanrc@yahoo.com.br blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), tag_latency); 103713418Sodanrc@yahoo.com.br 103812724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(), 103912724Snikos.nikoleris@arm.com blk ? "hit " + blk->print() : "miss"); 104012724Snikos.nikoleris@arm.com 104112724Snikos.nikoleris@arm.com if (pkt->req->isCacheMaintenance()) { 104212724Snikos.nikoleris@arm.com // A cache maintenance operation is always forwarded to the 104312724Snikos.nikoleris@arm.com // memory below even if the block is found in dirty state. 104412724Snikos.nikoleris@arm.com 104512724Snikos.nikoleris@arm.com // We defer any changes to the state of the block until we 104612724Snikos.nikoleris@arm.com // create and mark as in service the mshr for the downstream 104712724Snikos.nikoleris@arm.com // packet. 104813749Sodanrc@yahoo.com.br 104913749Sodanrc@yahoo.com.br // Calculate access latency on top of when the packet arrives. This 105013749Sodanrc@yahoo.com.br // takes into account the bus delay. 105113749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 105213749Sodanrc@yahoo.com.br 105312724Snikos.nikoleris@arm.com return false; 105412724Snikos.nikoleris@arm.com } 105512724Snikos.nikoleris@arm.com 105612724Snikos.nikoleris@arm.com if (pkt->isEviction()) { 105712724Snikos.nikoleris@arm.com // We check for presence of block in above caches before issuing 105812724Snikos.nikoleris@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 105912724Snikos.nikoleris@arm.com // possible cases can be of a CleanEvict packet coming from above 106012724Snikos.nikoleris@arm.com // encountering a Writeback generated in this cache peer cache and 106112724Snikos.nikoleris@arm.com // waiting in the write buffer. Cases of upper level peer caches 106212724Snikos.nikoleris@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 106312724Snikos.nikoleris@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 106412724Snikos.nikoleris@arm.com // by crossbar. 106512724Snikos.nikoleris@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 106612724Snikos.nikoleris@arm.com pkt->isSecure()); 106712724Snikos.nikoleris@arm.com if (wb_entry) { 106812724Snikos.nikoleris@arm.com assert(wb_entry->getNumTargets() == 1); 106912724Snikos.nikoleris@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 107012724Snikos.nikoleris@arm.com assert(wbPkt->isWriteback()); 107112724Snikos.nikoleris@arm.com 107212724Snikos.nikoleris@arm.com if (pkt->isCleanEviction()) { 107312724Snikos.nikoleris@arm.com // The CleanEvict and WritebackClean snoops into other 107412724Snikos.nikoleris@arm.com // peer caches of the same level while traversing the 107512724Snikos.nikoleris@arm.com // crossbar. If a copy of the block is found, the 107612724Snikos.nikoleris@arm.com // packet is deleted in the crossbar. Hence, none of 107712724Snikos.nikoleris@arm.com // the other upper level caches connected to this 107812724Snikos.nikoleris@arm.com // cache have the block, so we can clear the 107912724Snikos.nikoleris@arm.com // BLOCK_CACHED flag in the Writeback if set and 108012724Snikos.nikoleris@arm.com // discard the CleanEvict by returning true. 108112724Snikos.nikoleris@arm.com wbPkt->clearBlockCached(); 108213749Sodanrc@yahoo.com.br 108313749Sodanrc@yahoo.com.br // A clean evict does not need to access the data array 108413749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 108513749Sodanrc@yahoo.com.br 108612724Snikos.nikoleris@arm.com return true; 108712724Snikos.nikoleris@arm.com } else { 108812724Snikos.nikoleris@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 108912724Snikos.nikoleris@arm.com // Dirty writeback from above trumps our clean 109012724Snikos.nikoleris@arm.com // writeback... discard here 109112724Snikos.nikoleris@arm.com // Note: markInService will remove entry from writeback buffer. 109212724Snikos.nikoleris@arm.com markInService(wb_entry); 109312724Snikos.nikoleris@arm.com delete wbPkt; 109412724Snikos.nikoleris@arm.com } 109512724Snikos.nikoleris@arm.com } 109612724Snikos.nikoleris@arm.com } 109712724Snikos.nikoleris@arm.com 109812724Snikos.nikoleris@arm.com // Writeback handling is special case. We can write the block into 109912724Snikos.nikoleris@arm.com // the cache without having a writeable copy (or any copy at all). 110012724Snikos.nikoleris@arm.com if (pkt->isWriteback()) { 110112724Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 110212724Snikos.nikoleris@arm.com 110312724Snikos.nikoleris@arm.com // we could get a clean writeback while we are having 110412724Snikos.nikoleris@arm.com // outstanding accesses to a block, do the simple thing for 110512724Snikos.nikoleris@arm.com // now and drop the clean writeback so that we do not upset 110612724Snikos.nikoleris@arm.com // any ordering/decisions about ownership already taken 110712724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::WritebackClean && 110812724Snikos.nikoleris@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 110912724Snikos.nikoleris@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 111012724Snikos.nikoleris@arm.com "dropping\n", pkt->getAddr()); 111113749Sodanrc@yahoo.com.br 111213749Sodanrc@yahoo.com.br // A writeback searches for the block, then writes the data. 111313749Sodanrc@yahoo.com.br // As the writeback is being dropped, the data is not touched, 111413749Sodanrc@yahoo.com.br // and we just had to wait for the time to find a match in the 111513749Sodanrc@yahoo.com.br // MSHR. As of now assume a mshr queue search takes as long as 111613749Sodanrc@yahoo.com.br // a tag lookup for simplicity. 111713749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 111813749Sodanrc@yahoo.com.br 111912724Snikos.nikoleris@arm.com return true; 112012724Snikos.nikoleris@arm.com } 112112724Snikos.nikoleris@arm.com 112212724Snikos.nikoleris@arm.com if (!blk) { 112312724Snikos.nikoleris@arm.com // need to do a replacement 112414035Sodanrc@yahoo.com.br blk = allocateBlock(pkt, writebacks); 112512724Snikos.nikoleris@arm.com if (!blk) { 112612724Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to next level. 112712724Snikos.nikoleris@arm.com incMissCount(pkt); 112813749Sodanrc@yahoo.com.br 112913749Sodanrc@yahoo.com.br // A writeback searches for the block, then writes the data. 113013749Sodanrc@yahoo.com.br // As the block could not be found, it was a tag-only access. 113113749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 113213749Sodanrc@yahoo.com.br 113312724Snikos.nikoleris@arm.com return false; 113412724Snikos.nikoleris@arm.com } 113512724Snikos.nikoleris@arm.com 113613445Sodanrc@yahoo.com.br blk->status |= BlkReadable; 113713947Sodanrc@yahoo.com.br } else if (compressor) { 113813947Sodanrc@yahoo.com.br // This is an overwrite to an existing block, therefore we need 113913947Sodanrc@yahoo.com.br // to check for data expansion (i.e., block was compressed with 114013947Sodanrc@yahoo.com.br // a smaller size, and now it doesn't fit the entry anymore). 114113947Sodanrc@yahoo.com.br // If that is the case we might need to evict blocks. 114213947Sodanrc@yahoo.com.br if (!updateCompressionData(blk, pkt->getConstPtr<uint64_t>(), 114314035Sodanrc@yahoo.com.br writebacks)) { 114413947Sodanrc@yahoo.com.br // This is a failed data expansion (write), which happened 114513947Sodanrc@yahoo.com.br // after finding the replacement entries and accessing the 114613947Sodanrc@yahoo.com.br // block's data. There were no replaceable entries available 114713947Sodanrc@yahoo.com.br // to make room for the expanded block, and since it does not 114813947Sodanrc@yahoo.com.br // fit anymore and it has been properly updated to contain 114913947Sodanrc@yahoo.com.br // the new data, forward it to the next level 115013947Sodanrc@yahoo.com.br lat = calculateAccessLatency(blk, pkt->headerDelay, 115113947Sodanrc@yahoo.com.br tag_latency); 115213947Sodanrc@yahoo.com.br invalidateBlock(blk); 115313947Sodanrc@yahoo.com.br return false; 115413945Sodanrc@yahoo.com.br } 115512724Snikos.nikoleris@arm.com } 115613945Sodanrc@yahoo.com.br 115712724Snikos.nikoleris@arm.com // only mark the block dirty if we got a writeback command, 115812724Snikos.nikoleris@arm.com // and leave it as is for a clean writeback 115912724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 116012724Snikos.nikoleris@arm.com // TODO: the coherent cache can assert(!blk->isDirty()); 116112724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 116212724Snikos.nikoleris@arm.com } 116312724Snikos.nikoleris@arm.com // if the packet does not have sharers, it is passing 116412724Snikos.nikoleris@arm.com // writable, and we got the writeback in Modified or Exclusive 116512724Snikos.nikoleris@arm.com // state, if not we are in the Owned or Shared state 116612724Snikos.nikoleris@arm.com if (!pkt->hasSharers()) { 116712724Snikos.nikoleris@arm.com blk->status |= BlkWritable; 116812724Snikos.nikoleris@arm.com } 116912724Snikos.nikoleris@arm.com // nothing else to do; writeback doesn't expect response 117012724Snikos.nikoleris@arm.com assert(!pkt->needsResponse()); 117112724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 117212724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 117312724Snikos.nikoleris@arm.com incHitCount(pkt); 117413748Sodanrc@yahoo.com.br 117513765Sodanrc@yahoo.com.br // A writeback searches for the block, then writes the data 117613765Sodanrc@yahoo.com.br lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency); 117713765Sodanrc@yahoo.com.br 117813748Sodanrc@yahoo.com.br // When the packet metadata arrives, the tag lookup will be done while 117913748Sodanrc@yahoo.com.br // the payload is arriving. Then the block will be ready to access as 118013748Sodanrc@yahoo.com.br // soon as the fill is done 118113477Sodanrc@yahoo.com.br blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay + 118213748Sodanrc@yahoo.com.br std::max(cyclesToTicks(tag_latency), (uint64_t)pkt->payloadDelay)); 118313749Sodanrc@yahoo.com.br 118412724Snikos.nikoleris@arm.com return true; 118512724Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 118613749Sodanrc@yahoo.com.br // A CleanEvict does not need to access the data array 118713749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 118813749Sodanrc@yahoo.com.br 118912724Snikos.nikoleris@arm.com if (blk) { 119012724Snikos.nikoleris@arm.com // Found the block in the tags, need to stop CleanEvict from 119112724Snikos.nikoleris@arm.com // propagating further down the hierarchy. Returning true will 119212724Snikos.nikoleris@arm.com // treat the CleanEvict like a satisfied write request and delete 119312724Snikos.nikoleris@arm.com // it. 119412724Snikos.nikoleris@arm.com return true; 119512724Snikos.nikoleris@arm.com } 119612724Snikos.nikoleris@arm.com // We didn't find the block here, propagate the CleanEvict further 119712724Snikos.nikoleris@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 119812724Snikos.nikoleris@arm.com // like a Writeback which could not find a replaceable block so has to 119912724Snikos.nikoleris@arm.com // go to next level. 120012724Snikos.nikoleris@arm.com return false; 120112724Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 120212724Snikos.nikoleris@arm.com // WriteClean handling is a special case. We can allocate a 120312724Snikos.nikoleris@arm.com // block directly if it doesn't exist and we can update the 120412724Snikos.nikoleris@arm.com // block immediately. The WriteClean transfers the ownership 120512724Snikos.nikoleris@arm.com // of the block as well. 120612724Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 120712724Snikos.nikoleris@arm.com 120812724Snikos.nikoleris@arm.com if (!blk) { 120912724Snikos.nikoleris@arm.com if (pkt->writeThrough()) { 121013749Sodanrc@yahoo.com.br // A writeback searches for the block, then writes the data. 121113749Sodanrc@yahoo.com.br // As the block could not be found, it was a tag-only access. 121213749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 121313749Sodanrc@yahoo.com.br 121412724Snikos.nikoleris@arm.com // if this is a write through packet, we don't try to 121512724Snikos.nikoleris@arm.com // allocate if the block is not present 121612724Snikos.nikoleris@arm.com return false; 121712724Snikos.nikoleris@arm.com } else { 121812724Snikos.nikoleris@arm.com // a writeback that misses needs to allocate a new block 121914035Sodanrc@yahoo.com.br blk = allocateBlock(pkt, writebacks); 122012724Snikos.nikoleris@arm.com if (!blk) { 122112724Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to 122212724Snikos.nikoleris@arm.com // next level. 122312724Snikos.nikoleris@arm.com incMissCount(pkt); 122413749Sodanrc@yahoo.com.br 122513749Sodanrc@yahoo.com.br // A writeback searches for the block, then writes the 122613749Sodanrc@yahoo.com.br // data. As the block could not be found, it was a tag-only 122713749Sodanrc@yahoo.com.br // access. 122813749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, 122913749Sodanrc@yahoo.com.br tag_latency); 123013749Sodanrc@yahoo.com.br 123112724Snikos.nikoleris@arm.com return false; 123212724Snikos.nikoleris@arm.com } 123312724Snikos.nikoleris@arm.com 123413445Sodanrc@yahoo.com.br blk->status |= BlkReadable; 123512724Snikos.nikoleris@arm.com } 123613947Sodanrc@yahoo.com.br } else if (compressor) { 123713947Sodanrc@yahoo.com.br // This is an overwrite to an existing block, therefore we need 123813947Sodanrc@yahoo.com.br // to check for data expansion (i.e., block was compressed with 123913947Sodanrc@yahoo.com.br // a smaller size, and now it doesn't fit the entry anymore). 124013947Sodanrc@yahoo.com.br // If that is the case we might need to evict blocks. 124113947Sodanrc@yahoo.com.br if (!updateCompressionData(blk, pkt->getConstPtr<uint64_t>(), 124214035Sodanrc@yahoo.com.br writebacks)) { 124313947Sodanrc@yahoo.com.br // This is a failed data expansion (write), which happened 124413947Sodanrc@yahoo.com.br // after finding the replacement entries and accessing the 124513947Sodanrc@yahoo.com.br // block's data. There were no replaceable entries available 124613947Sodanrc@yahoo.com.br // to make room for the expanded block, and since it does not 124713947Sodanrc@yahoo.com.br // fit anymore and it has been properly updated to contain 124813947Sodanrc@yahoo.com.br // the new data, forward it to the next level 124913947Sodanrc@yahoo.com.br lat = calculateAccessLatency(blk, pkt->headerDelay, 125013947Sodanrc@yahoo.com.br tag_latency); 125113947Sodanrc@yahoo.com.br invalidateBlock(blk); 125213947Sodanrc@yahoo.com.br return false; 125313945Sodanrc@yahoo.com.br } 125412724Snikos.nikoleris@arm.com } 125512724Snikos.nikoleris@arm.com 125612724Snikos.nikoleris@arm.com // at this point either this is a writeback or a write-through 125712724Snikos.nikoleris@arm.com // write clean operation and the block is already in this 125812724Snikos.nikoleris@arm.com // cache, we need to update the data and the block flags 125912724Snikos.nikoleris@arm.com assert(blk); 126012724Snikos.nikoleris@arm.com // TODO: the coherent cache can assert(!blk->isDirty()); 126112724Snikos.nikoleris@arm.com if (!pkt->writeThrough()) { 126212724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 126312724Snikos.nikoleris@arm.com } 126412724Snikos.nikoleris@arm.com // nothing else to do; writeback doesn't expect response 126512724Snikos.nikoleris@arm.com assert(!pkt->needsResponse()); 126612724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 126712724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 126812724Snikos.nikoleris@arm.com 126912724Snikos.nikoleris@arm.com incHitCount(pkt); 127013748Sodanrc@yahoo.com.br 127113765Sodanrc@yahoo.com.br // A writeback searches for the block, then writes the data 127213765Sodanrc@yahoo.com.br lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency); 127313765Sodanrc@yahoo.com.br 127413748Sodanrc@yahoo.com.br // When the packet metadata arrives, the tag lookup will be done while 127513748Sodanrc@yahoo.com.br // the payload is arriving. Then the block will be ready to access as 127613748Sodanrc@yahoo.com.br // soon as the fill is done 127713477Sodanrc@yahoo.com.br blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay + 127813748Sodanrc@yahoo.com.br std::max(cyclesToTicks(tag_latency), (uint64_t)pkt->payloadDelay)); 127913748Sodanrc@yahoo.com.br 128013947Sodanrc@yahoo.com.br // If this a write-through packet it will be sent to cache below 128112724Snikos.nikoleris@arm.com return !pkt->writeThrough(); 128212724Snikos.nikoleris@arm.com } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 128312724Snikos.nikoleris@arm.com blk->isReadable())) { 128412724Snikos.nikoleris@arm.com // OK to satisfy access 128512724Snikos.nikoleris@arm.com incHitCount(pkt); 128612724Snikos.nikoleris@arm.com 128713749Sodanrc@yahoo.com.br // Calculate access latency based on the need to access the data array 128813749Sodanrc@yahoo.com.br if (pkt->isRead() || pkt->isWrite()) { 128913749Sodanrc@yahoo.com.br lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency); 129013945Sodanrc@yahoo.com.br 129113945Sodanrc@yahoo.com.br // When a block is compressed, it must first be decompressed 129213945Sodanrc@yahoo.com.br // before being read. This adds to the access latency. 129313945Sodanrc@yahoo.com.br if (compressor && pkt->isRead()) { 129413945Sodanrc@yahoo.com.br lat += compressor->getDecompressionLatency(blk); 129513945Sodanrc@yahoo.com.br } 129613749Sodanrc@yahoo.com.br } else { 129713749Sodanrc@yahoo.com.br lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency); 129813749Sodanrc@yahoo.com.br } 129913749Sodanrc@yahoo.com.br 130013765Sodanrc@yahoo.com.br satisfyRequest(pkt, blk); 130113765Sodanrc@yahoo.com.br maintainClusivity(pkt->fromCache(), blk); 130213765Sodanrc@yahoo.com.br 130312724Snikos.nikoleris@arm.com return true; 130412724Snikos.nikoleris@arm.com } 130512724Snikos.nikoleris@arm.com 130612724Snikos.nikoleris@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 130712724Snikos.nikoleris@arm.com // or have block but need writable 130812724Snikos.nikoleris@arm.com 130912724Snikos.nikoleris@arm.com incMissCount(pkt); 131012724Snikos.nikoleris@arm.com 131113749Sodanrc@yahoo.com.br lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency); 131213749Sodanrc@yahoo.com.br 131312724Snikos.nikoleris@arm.com if (!blk && pkt->isLLSC() && pkt->isWrite()) { 131412724Snikos.nikoleris@arm.com // complete miss on store conditional... just give up now 131512724Snikos.nikoleris@arm.com pkt->req->setExtraData(0); 131612724Snikos.nikoleris@arm.com return true; 131712724Snikos.nikoleris@arm.com } 131812724Snikos.nikoleris@arm.com 131912724Snikos.nikoleris@arm.com return false; 132012724Snikos.nikoleris@arm.com} 132112724Snikos.nikoleris@arm.com 132212724Snikos.nikoleris@arm.comvoid 132312724Snikos.nikoleris@arm.comBaseCache::maintainClusivity(bool from_cache, CacheBlk *blk) 132412724Snikos.nikoleris@arm.com{ 132512724Snikos.nikoleris@arm.com if (from_cache && blk && blk->isValid() && !blk->isDirty() && 132612724Snikos.nikoleris@arm.com clusivity == Enums::mostly_excl) { 132712724Snikos.nikoleris@arm.com // if we have responded to a cache, and our block is still 132812724Snikos.nikoleris@arm.com // valid, but not dirty, and this cache is mostly exclusive 132912724Snikos.nikoleris@arm.com // with respect to the cache above, drop the block 133012724Snikos.nikoleris@arm.com invalidateBlock(blk); 133112724Snikos.nikoleris@arm.com } 133212724Snikos.nikoleris@arm.com} 133312724Snikos.nikoleris@arm.com 133412724Snikos.nikoleris@arm.comCacheBlk* 133514035Sodanrc@yahoo.com.brBaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 133614035Sodanrc@yahoo.com.br bool allocate) 133712724Snikos.nikoleris@arm.com{ 133813350Snikos.nikoleris@arm.com assert(pkt->isResponse()); 133912724Snikos.nikoleris@arm.com Addr addr = pkt->getAddr(); 134012724Snikos.nikoleris@arm.com bool is_secure = pkt->isSecure(); 134112724Snikos.nikoleris@arm.com#if TRACING_ON 134212724Snikos.nikoleris@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 134312724Snikos.nikoleris@arm.com#endif 134412724Snikos.nikoleris@arm.com 134512724Snikos.nikoleris@arm.com // When handling a fill, we should have no writes to this line. 134612724Snikos.nikoleris@arm.com assert(addr == pkt->getBlockAddr(blkSize)); 134712724Snikos.nikoleris@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 134812724Snikos.nikoleris@arm.com 134912724Snikos.nikoleris@arm.com if (!blk) { 135012724Snikos.nikoleris@arm.com // better have read new data... 135113350Snikos.nikoleris@arm.com assert(pkt->hasData() || pkt->cmd == MemCmd::InvalidateResp); 135212724Snikos.nikoleris@arm.com 135314035Sodanrc@yahoo.com.br // need to do a replacement if allocating, otherwise we stick 135414035Sodanrc@yahoo.com.br // with the temporary storage 135514035Sodanrc@yahoo.com.br blk = allocate ? allocateBlock(pkt, writebacks) : nullptr; 135612724Snikos.nikoleris@arm.com 135712724Snikos.nikoleris@arm.com if (!blk) { 135812724Snikos.nikoleris@arm.com // No replaceable block or a mostly exclusive 135912724Snikos.nikoleris@arm.com // cache... just use temporary storage to complete the 136012724Snikos.nikoleris@arm.com // current request and then get rid of it 136112724Snikos.nikoleris@arm.com blk = tempBlock; 136212730Sodanrc@yahoo.com.br tempBlock->insert(addr, is_secure); 136312724Snikos.nikoleris@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 136412724Snikos.nikoleris@arm.com is_secure ? "s" : "ns"); 136512724Snikos.nikoleris@arm.com } 136612724Snikos.nikoleris@arm.com } else { 136712724Snikos.nikoleris@arm.com // existing block... probably an upgrade 136812724Snikos.nikoleris@arm.com // don't clear block status... if block is already dirty we 136912724Snikos.nikoleris@arm.com // don't want to lose that 137012724Snikos.nikoleris@arm.com } 137112724Snikos.nikoleris@arm.com 137213445Sodanrc@yahoo.com.br // Block is guaranteed to be valid at this point 137313445Sodanrc@yahoo.com.br assert(blk->isValid()); 137413445Sodanrc@yahoo.com.br assert(blk->isSecure() == is_secure); 137513445Sodanrc@yahoo.com.br assert(regenerateBlkAddr(blk) == addr); 137613445Sodanrc@yahoo.com.br 137713445Sodanrc@yahoo.com.br blk->status |= BlkReadable; 137812724Snikos.nikoleris@arm.com 137912724Snikos.nikoleris@arm.com // sanity check for whole-line writes, which should always be 138012724Snikos.nikoleris@arm.com // marked as writable as part of the fill, and then later marked 138112724Snikos.nikoleris@arm.com // dirty as part of satisfyRequest 138213350Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::InvalidateResp) { 138312724Snikos.nikoleris@arm.com assert(!pkt->hasSharers()); 138412724Snikos.nikoleris@arm.com } 138512724Snikos.nikoleris@arm.com 138612724Snikos.nikoleris@arm.com // here we deal with setting the appropriate state of the line, 138712724Snikos.nikoleris@arm.com // and we start by looking at the hasSharers flag, and ignore the 138812724Snikos.nikoleris@arm.com // cacheResponding flag (normally signalling dirty data) if the 138912724Snikos.nikoleris@arm.com // packet has sharers, thus the line is never allocated as Owned 139012724Snikos.nikoleris@arm.com // (dirty but not writable), and always ends up being either 139112724Snikos.nikoleris@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 139212724Snikos.nikoleris@arm.com // for more details 139312724Snikos.nikoleris@arm.com if (!pkt->hasSharers()) { 139412724Snikos.nikoleris@arm.com // we could get a writable line from memory (rather than a 139512724Snikos.nikoleris@arm.com // cache) even in a read-only cache, note that we set this bit 139612724Snikos.nikoleris@arm.com // even for a read-only cache, possibly revisit this decision 139712724Snikos.nikoleris@arm.com blk->status |= BlkWritable; 139812724Snikos.nikoleris@arm.com 139912724Snikos.nikoleris@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 140012724Snikos.nikoleris@arm.com // cache that had the block in Modified or Owned state) 140112724Snikos.nikoleris@arm.com if (pkt->cacheResponding()) { 140212724Snikos.nikoleris@arm.com // we got the block in Modified state, and invalidated the 140312724Snikos.nikoleris@arm.com // owners copy 140412724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 140512724Snikos.nikoleris@arm.com 140612724Snikos.nikoleris@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 140712724Snikos.nikoleris@arm.com "in read-only cache %s\n", name()); 140813932Snikos.nikoleris@arm.com 140912724Snikos.nikoleris@arm.com } 141012724Snikos.nikoleris@arm.com } 141112724Snikos.nikoleris@arm.com 141212724Snikos.nikoleris@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 141312724Snikos.nikoleris@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 141412724Snikos.nikoleris@arm.com 141512724Snikos.nikoleris@arm.com // if we got new data, copy it in (checking for a read response 141612724Snikos.nikoleris@arm.com // and a response that has data is the same in the end) 141712724Snikos.nikoleris@arm.com if (pkt->isRead()) { 141812724Snikos.nikoleris@arm.com // sanity checks 141912724Snikos.nikoleris@arm.com assert(pkt->hasData()); 142012724Snikos.nikoleris@arm.com assert(pkt->getSize() == blkSize); 142112724Snikos.nikoleris@arm.com 142212724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 142312724Snikos.nikoleris@arm.com } 142413750Sodanrc@yahoo.com.br // The block will be ready when the payload arrives and the fill is done 142513750Sodanrc@yahoo.com.br blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay + 142613750Sodanrc@yahoo.com.br pkt->payloadDelay); 142712724Snikos.nikoleris@arm.com 142812724Snikos.nikoleris@arm.com return blk; 142912724Snikos.nikoleris@arm.com} 143012724Snikos.nikoleris@arm.com 143112724Snikos.nikoleris@arm.comCacheBlk* 143214035Sodanrc@yahoo.com.brBaseCache::allocateBlock(const PacketPtr pkt, PacketList &writebacks) 143312724Snikos.nikoleris@arm.com{ 143412754Sodanrc@yahoo.com.br // Get address 143512754Sodanrc@yahoo.com.br const Addr addr = pkt->getAddr(); 143612754Sodanrc@yahoo.com.br 143712754Sodanrc@yahoo.com.br // Get secure bit 143812754Sodanrc@yahoo.com.br const bool is_secure = pkt->isSecure(); 143912754Sodanrc@yahoo.com.br 144013945Sodanrc@yahoo.com.br // Block size and compression related access latency. Only relevant if 144113945Sodanrc@yahoo.com.br // using a compressor, otherwise there is no extra delay, and the block 144213945Sodanrc@yahoo.com.br // is fully sized 144313941Sodanrc@yahoo.com.br std::size_t blk_size_bits = blkSize*8; 144413945Sodanrc@yahoo.com.br Cycles compression_lat = Cycles(0); 144513945Sodanrc@yahoo.com.br Cycles decompression_lat = Cycles(0); 144613945Sodanrc@yahoo.com.br 144713945Sodanrc@yahoo.com.br // If a compressor is being used, it is called to compress data before 144813945Sodanrc@yahoo.com.br // insertion. Although in Gem5 the data is stored uncompressed, even if a 144913945Sodanrc@yahoo.com.br // compressor is used, the compression/decompression methods are called to 145013945Sodanrc@yahoo.com.br // calculate the amount of extra cycles needed to read or write compressed 145113945Sodanrc@yahoo.com.br // blocks. 145213945Sodanrc@yahoo.com.br if (compressor) { 145313945Sodanrc@yahoo.com.br compressor->compress(pkt->getConstPtr<uint64_t>(), compression_lat, 145413945Sodanrc@yahoo.com.br decompression_lat, blk_size_bits); 145513945Sodanrc@yahoo.com.br } 145613941Sodanrc@yahoo.com.br 145712724Snikos.nikoleris@arm.com // Find replacement victim 145812744Sodanrc@yahoo.com.br std::vector<CacheBlk*> evict_blks; 145913941Sodanrc@yahoo.com.br CacheBlk *victim = tags->findVictim(addr, is_secure, blk_size_bits, 146013941Sodanrc@yahoo.com.br evict_blks); 146112724Snikos.nikoleris@arm.com 146212724Snikos.nikoleris@arm.com // It is valid to return nullptr if there is no victim 146312744Sodanrc@yahoo.com.br if (!victim) 146412724Snikos.nikoleris@arm.com return nullptr; 146512724Snikos.nikoleris@arm.com 146613222Sodanrc@yahoo.com.br // Print victim block's information 146713222Sodanrc@yahoo.com.br DPRINTF(CacheRepl, "Replacement victim: %s\n", victim->print()); 146813222Sodanrc@yahoo.com.br 146912744Sodanrc@yahoo.com.br // Check for transient state allocations. If any of the entries listed 147012744Sodanrc@yahoo.com.br // for eviction has a transient state, the allocation fails 147113866Sodanrc@yahoo.com.br bool replacement = false; 147212744Sodanrc@yahoo.com.br for (const auto& blk : evict_blks) { 147312744Sodanrc@yahoo.com.br if (blk->isValid()) { 147413866Sodanrc@yahoo.com.br replacement = true; 147513866Sodanrc@yahoo.com.br 147612744Sodanrc@yahoo.com.br Addr repl_addr = regenerateBlkAddr(blk); 147712744Sodanrc@yahoo.com.br MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 147812744Sodanrc@yahoo.com.br if (repl_mshr) { 147912744Sodanrc@yahoo.com.br // must be an outstanding upgrade or clean request 148012744Sodanrc@yahoo.com.br // on a block we're about to replace... 148112744Sodanrc@yahoo.com.br assert((!blk->isWritable() && repl_mshr->needsWritable()) || 148212744Sodanrc@yahoo.com.br repl_mshr->isCleaning()); 148312724Snikos.nikoleris@arm.com 148412744Sodanrc@yahoo.com.br // too hard to replace block with transient state 148512744Sodanrc@yahoo.com.br // allocation failed, block not inserted 148612744Sodanrc@yahoo.com.br return nullptr; 148712744Sodanrc@yahoo.com.br } 148812744Sodanrc@yahoo.com.br } 148912744Sodanrc@yahoo.com.br } 149012744Sodanrc@yahoo.com.br 149112744Sodanrc@yahoo.com.br // The victim will be replaced by a new entry, so increase the replacement 149212744Sodanrc@yahoo.com.br // counter if a valid block is being replaced 149313866Sodanrc@yahoo.com.br if (replacement) { 149413866Sodanrc@yahoo.com.br // Evict valid blocks associated to this victim block 149513863Sodanrc@yahoo.com.br for (const auto& blk : evict_blks) { 149613863Sodanrc@yahoo.com.br if (blk->isValid()) { 149713863Sodanrc@yahoo.com.br DPRINTF(CacheRepl, "Evicting %s (%#llx) to make room for " \ 149813863Sodanrc@yahoo.com.br "%#llx (%s)\n", blk->print(), regenerateBlkAddr(blk), 149913863Sodanrc@yahoo.com.br addr, is_secure); 150013866Sodanrc@yahoo.com.br 150113866Sodanrc@yahoo.com.br if (blk->wasPrefetched()) { 150213866Sodanrc@yahoo.com.br unusedPrefetches++; 150313866Sodanrc@yahoo.com.br } 150413866Sodanrc@yahoo.com.br 150514035Sodanrc@yahoo.com.br evictBlock(blk, writebacks); 150613863Sodanrc@yahoo.com.br } 150713863Sodanrc@yahoo.com.br } 150812744Sodanrc@yahoo.com.br 150912744Sodanrc@yahoo.com.br replacements++; 151012744Sodanrc@yahoo.com.br } 151112744Sodanrc@yahoo.com.br 151213945Sodanrc@yahoo.com.br // If using a compressor, set compression data. This must be done before 151313945Sodanrc@yahoo.com.br // block insertion, as compressed tags use this information. 151413945Sodanrc@yahoo.com.br if (compressor) { 151513945Sodanrc@yahoo.com.br compressor->setSizeBits(victim, blk_size_bits); 151613945Sodanrc@yahoo.com.br compressor->setDecompressionLatency(victim, decompression_lat); 151713945Sodanrc@yahoo.com.br } 151813945Sodanrc@yahoo.com.br 151912754Sodanrc@yahoo.com.br // Insert new block at victimized entry 152013752Sodanrc@yahoo.com.br tags->insertBlock(pkt, victim); 152112754Sodanrc@yahoo.com.br 152212744Sodanrc@yahoo.com.br return victim; 152312724Snikos.nikoleris@arm.com} 152412724Snikos.nikoleris@arm.com 152512724Snikos.nikoleris@arm.comvoid 152612724Snikos.nikoleris@arm.comBaseCache::invalidateBlock(CacheBlk *blk) 152712724Snikos.nikoleris@arm.com{ 152813376Sodanrc@yahoo.com.br // If handling a block present in the Tags, let it do its invalidation 152913376Sodanrc@yahoo.com.br // process, which will update stats and invalidate the block itself 153013376Sodanrc@yahoo.com.br if (blk != tempBlock) { 153112724Snikos.nikoleris@arm.com tags->invalidate(blk); 153213376Sodanrc@yahoo.com.br } else { 153313376Sodanrc@yahoo.com.br tempBlock->invalidate(); 153413376Sodanrc@yahoo.com.br } 153512724Snikos.nikoleris@arm.com} 153612724Snikos.nikoleris@arm.com 153713358Sodanrc@yahoo.com.brvoid 153814035Sodanrc@yahoo.com.brBaseCache::evictBlock(CacheBlk *blk, PacketList &writebacks) 153913358Sodanrc@yahoo.com.br{ 154013358Sodanrc@yahoo.com.br PacketPtr pkt = evictBlock(blk); 154113358Sodanrc@yahoo.com.br if (pkt) { 154214035Sodanrc@yahoo.com.br writebacks.push_back(pkt); 154313358Sodanrc@yahoo.com.br } 154413358Sodanrc@yahoo.com.br} 154513358Sodanrc@yahoo.com.br 154612724Snikos.nikoleris@arm.comPacketPtr 154712724Snikos.nikoleris@arm.comBaseCache::writebackBlk(CacheBlk *blk) 154812724Snikos.nikoleris@arm.com{ 154912724Snikos.nikoleris@arm.com chatty_assert(!isReadOnly || writebackClean, 155012724Snikos.nikoleris@arm.com "Writeback from read-only cache"); 155112724Snikos.nikoleris@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 155212724Snikos.nikoleris@arm.com 155312724Snikos.nikoleris@arm.com writebacks[Request::wbMasterId]++; 155412724Snikos.nikoleris@arm.com 155512749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 155612749Sgiacomo.travaglini@arm.com regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 155712749Sgiacomo.travaglini@arm.com 155812724Snikos.nikoleris@arm.com if (blk->isSecure()) 155912724Snikos.nikoleris@arm.com req->setFlags(Request::SECURE); 156012724Snikos.nikoleris@arm.com 156112724Snikos.nikoleris@arm.com req->taskId(blk->task_id); 156212724Snikos.nikoleris@arm.com 156312724Snikos.nikoleris@arm.com PacketPtr pkt = 156412724Snikos.nikoleris@arm.com new Packet(req, blk->isDirty() ? 156512724Snikos.nikoleris@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 156612724Snikos.nikoleris@arm.com 156712724Snikos.nikoleris@arm.com DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 156812724Snikos.nikoleris@arm.com pkt->print(), blk->isWritable(), blk->isDirty()); 156912724Snikos.nikoleris@arm.com 157012724Snikos.nikoleris@arm.com if (blk->isWritable()) { 157112724Snikos.nikoleris@arm.com // not asserting shared means we pass the block in modified 157212724Snikos.nikoleris@arm.com // state, mark our own block non-writeable 157312724Snikos.nikoleris@arm.com blk->status &= ~BlkWritable; 157412724Snikos.nikoleris@arm.com } else { 157512724Snikos.nikoleris@arm.com // we are in the Owned state, tell the receiver 157612724Snikos.nikoleris@arm.com pkt->setHasSharers(); 157712724Snikos.nikoleris@arm.com } 157812724Snikos.nikoleris@arm.com 157912724Snikos.nikoleris@arm.com // make sure the block is not marked dirty 158012724Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 158112724Snikos.nikoleris@arm.com 158212724Snikos.nikoleris@arm.com pkt->allocate(); 158312724Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 158412724Snikos.nikoleris@arm.com 158513945Sodanrc@yahoo.com.br // When a block is compressed, it must first be decompressed before being 158613945Sodanrc@yahoo.com.br // sent for writeback. 158713945Sodanrc@yahoo.com.br if (compressor) { 158813945Sodanrc@yahoo.com.br pkt->payloadDelay = compressor->getDecompressionLatency(blk); 158913945Sodanrc@yahoo.com.br } 159013945Sodanrc@yahoo.com.br 159112724Snikos.nikoleris@arm.com return pkt; 159212724Snikos.nikoleris@arm.com} 159312724Snikos.nikoleris@arm.com 159412724Snikos.nikoleris@arm.comPacketPtr 159512724Snikos.nikoleris@arm.comBaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id) 159612724Snikos.nikoleris@arm.com{ 159712749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 159812749Sgiacomo.travaglini@arm.com regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 159912749Sgiacomo.travaglini@arm.com 160012724Snikos.nikoleris@arm.com if (blk->isSecure()) { 160112724Snikos.nikoleris@arm.com req->setFlags(Request::SECURE); 160212724Snikos.nikoleris@arm.com } 160312724Snikos.nikoleris@arm.com req->taskId(blk->task_id); 160412724Snikos.nikoleris@arm.com 160512724Snikos.nikoleris@arm.com PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id); 160612724Snikos.nikoleris@arm.com 160712724Snikos.nikoleris@arm.com if (dest) { 160812724Snikos.nikoleris@arm.com req->setFlags(dest); 160912724Snikos.nikoleris@arm.com pkt->setWriteThrough(); 161012724Snikos.nikoleris@arm.com } 161112724Snikos.nikoleris@arm.com 161212724Snikos.nikoleris@arm.com DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 161312724Snikos.nikoleris@arm.com blk->isWritable(), blk->isDirty()); 161412724Snikos.nikoleris@arm.com 161512724Snikos.nikoleris@arm.com if (blk->isWritable()) { 161612724Snikos.nikoleris@arm.com // not asserting shared means we pass the block in modified 161712724Snikos.nikoleris@arm.com // state, mark our own block non-writeable 161812724Snikos.nikoleris@arm.com blk->status &= ~BlkWritable; 161912724Snikos.nikoleris@arm.com } else { 162012724Snikos.nikoleris@arm.com // we are in the Owned state, tell the receiver 162112724Snikos.nikoleris@arm.com pkt->setHasSharers(); 162212724Snikos.nikoleris@arm.com } 162312724Snikos.nikoleris@arm.com 162412724Snikos.nikoleris@arm.com // make sure the block is not marked dirty 162512724Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 162612724Snikos.nikoleris@arm.com 162712724Snikos.nikoleris@arm.com pkt->allocate(); 162812724Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 162912724Snikos.nikoleris@arm.com 163013945Sodanrc@yahoo.com.br // When a block is compressed, it must first be decompressed before being 163113945Sodanrc@yahoo.com.br // sent for writeback. 163213945Sodanrc@yahoo.com.br if (compressor) { 163313945Sodanrc@yahoo.com.br pkt->payloadDelay = compressor->getDecompressionLatency(blk); 163413945Sodanrc@yahoo.com.br } 163513945Sodanrc@yahoo.com.br 163612724Snikos.nikoleris@arm.com return pkt; 163712724Snikos.nikoleris@arm.com} 163812724Snikos.nikoleris@arm.com 163912724Snikos.nikoleris@arm.com 164012724Snikos.nikoleris@arm.comvoid 164112724Snikos.nikoleris@arm.comBaseCache::memWriteback() 164212724Snikos.nikoleris@arm.com{ 164312728Snikos.nikoleris@arm.com tags->forEachBlk([this](CacheBlk &blk) { writebackVisitor(blk); }); 164412724Snikos.nikoleris@arm.com} 164512724Snikos.nikoleris@arm.com 164612724Snikos.nikoleris@arm.comvoid 164712724Snikos.nikoleris@arm.comBaseCache::memInvalidate() 164812724Snikos.nikoleris@arm.com{ 164912728Snikos.nikoleris@arm.com tags->forEachBlk([this](CacheBlk &blk) { invalidateVisitor(blk); }); 165012724Snikos.nikoleris@arm.com} 165112724Snikos.nikoleris@arm.com 165212724Snikos.nikoleris@arm.combool 165312724Snikos.nikoleris@arm.comBaseCache::isDirty() const 165412724Snikos.nikoleris@arm.com{ 165512728Snikos.nikoleris@arm.com return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); }); 165612724Snikos.nikoleris@arm.com} 165712724Snikos.nikoleris@arm.com 165813416Sjavier.bueno@metempsy.combool 165913416Sjavier.bueno@metempsy.comBaseCache::coalesce() const 166013416Sjavier.bueno@metempsy.com{ 166113416Sjavier.bueno@metempsy.com return writeAllocator && writeAllocator->coalesce(); 166213416Sjavier.bueno@metempsy.com} 166313416Sjavier.bueno@metempsy.com 166412728Snikos.nikoleris@arm.comvoid 166512724Snikos.nikoleris@arm.comBaseCache::writebackVisitor(CacheBlk &blk) 166612724Snikos.nikoleris@arm.com{ 166712724Snikos.nikoleris@arm.com if (blk.isDirty()) { 166812724Snikos.nikoleris@arm.com assert(blk.isValid()); 166912724Snikos.nikoleris@arm.com 167012749Sgiacomo.travaglini@arm.com RequestPtr request = std::make_shared<Request>( 167112749Sgiacomo.travaglini@arm.com regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId); 167212749Sgiacomo.travaglini@arm.com 167312749Sgiacomo.travaglini@arm.com request->taskId(blk.task_id); 167412724Snikos.nikoleris@arm.com if (blk.isSecure()) { 167512749Sgiacomo.travaglini@arm.com request->setFlags(Request::SECURE); 167612724Snikos.nikoleris@arm.com } 167712724Snikos.nikoleris@arm.com 167812749Sgiacomo.travaglini@arm.com Packet packet(request, MemCmd::WriteReq); 167912724Snikos.nikoleris@arm.com packet.dataStatic(blk.data); 168012724Snikos.nikoleris@arm.com 168112724Snikos.nikoleris@arm.com memSidePort.sendFunctional(&packet); 168212724Snikos.nikoleris@arm.com 168312724Snikos.nikoleris@arm.com blk.status &= ~BlkDirty; 168412724Snikos.nikoleris@arm.com } 168512724Snikos.nikoleris@arm.com} 168612724Snikos.nikoleris@arm.com 168712728Snikos.nikoleris@arm.comvoid 168812724Snikos.nikoleris@arm.comBaseCache::invalidateVisitor(CacheBlk &blk) 168912724Snikos.nikoleris@arm.com{ 169012724Snikos.nikoleris@arm.com if (blk.isDirty()) 169112724Snikos.nikoleris@arm.com warn_once("Invalidating dirty cache lines. " \ 169212724Snikos.nikoleris@arm.com "Expect things to break.\n"); 169312724Snikos.nikoleris@arm.com 169412724Snikos.nikoleris@arm.com if (blk.isValid()) { 169512724Snikos.nikoleris@arm.com assert(!blk.isDirty()); 169612724Snikos.nikoleris@arm.com invalidateBlock(&blk); 169712724Snikos.nikoleris@arm.com } 169812724Snikos.nikoleris@arm.com} 169912724Snikos.nikoleris@arm.com 170012724Snikos.nikoleris@arm.comTick 170112724Snikos.nikoleris@arm.comBaseCache::nextQueueReadyTime() const 170212724Snikos.nikoleris@arm.com{ 170312724Snikos.nikoleris@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 170412724Snikos.nikoleris@arm.com writeBuffer.nextReadyTime()); 170512724Snikos.nikoleris@arm.com 170612724Snikos.nikoleris@arm.com // Don't signal prefetch ready time if no MSHRs available 170712724Snikos.nikoleris@arm.com // Will signal once enoguh MSHRs are deallocated 170812724Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 170912724Snikos.nikoleris@arm.com nextReady = std::min(nextReady, 171012724Snikos.nikoleris@arm.com prefetcher->nextPrefetchReadyTime()); 171112724Snikos.nikoleris@arm.com } 171212724Snikos.nikoleris@arm.com 171312724Snikos.nikoleris@arm.com return nextReady; 171412724Snikos.nikoleris@arm.com} 171512724Snikos.nikoleris@arm.com 171612724Snikos.nikoleris@arm.com 171712724Snikos.nikoleris@arm.combool 171812724Snikos.nikoleris@arm.comBaseCache::sendMSHRQueuePacket(MSHR* mshr) 171912724Snikos.nikoleris@arm.com{ 172012724Snikos.nikoleris@arm.com assert(mshr); 172112724Snikos.nikoleris@arm.com 172212724Snikos.nikoleris@arm.com // use request from 1st target 172312724Snikos.nikoleris@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 172412724Snikos.nikoleris@arm.com 172512724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 172612724Snikos.nikoleris@arm.com 172713352Snikos.nikoleris@arm.com // if the cache is in write coalescing mode or (additionally) in 172813352Snikos.nikoleris@arm.com // no allocation mode, and we have a write packet with an MSHR 172913352Snikos.nikoleris@arm.com // that is not a whole-line write (due to incompatible flags etc), 173013352Snikos.nikoleris@arm.com // then reset the write mode 173113352Snikos.nikoleris@arm.com if (writeAllocator && writeAllocator->coalesce() && tgt_pkt->isWrite()) { 173213352Snikos.nikoleris@arm.com if (!mshr->isWholeLineWrite()) { 173313352Snikos.nikoleris@arm.com // if we are currently write coalescing, hold on the 173413352Snikos.nikoleris@arm.com // MSHR as many cycles extra as we need to completely 173513352Snikos.nikoleris@arm.com // write a cache line 173613352Snikos.nikoleris@arm.com if (writeAllocator->delay(mshr->blkAddr)) { 173713352Snikos.nikoleris@arm.com Tick delay = blkSize / tgt_pkt->getSize() * clockPeriod(); 173813352Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "Delaying pkt %s %llu ticks to allow " 173913352Snikos.nikoleris@arm.com "for write coalescing\n", tgt_pkt->print(), delay); 174013352Snikos.nikoleris@arm.com mshrQueue.delay(mshr, delay); 174113352Snikos.nikoleris@arm.com return false; 174213352Snikos.nikoleris@arm.com } else { 174313352Snikos.nikoleris@arm.com writeAllocator->reset(); 174413352Snikos.nikoleris@arm.com } 174513352Snikos.nikoleris@arm.com } else { 174613352Snikos.nikoleris@arm.com writeAllocator->resetDelay(mshr->blkAddr); 174713352Snikos.nikoleris@arm.com } 174813352Snikos.nikoleris@arm.com } 174913352Snikos.nikoleris@arm.com 175012724Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 175112724Snikos.nikoleris@arm.com 175212724Snikos.nikoleris@arm.com // either a prefetch that is not present upstream, or a normal 175312724Snikos.nikoleris@arm.com // MSHR request, proceed to get the packet to send downstream 175413350Snikos.nikoleris@arm.com PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable(), 175513350Snikos.nikoleris@arm.com mshr->isWholeLineWrite()); 175612724Snikos.nikoleris@arm.com 175712724Snikos.nikoleris@arm.com mshr->isForward = (pkt == nullptr); 175812724Snikos.nikoleris@arm.com 175912724Snikos.nikoleris@arm.com if (mshr->isForward) { 176012724Snikos.nikoleris@arm.com // not a cache block request, but a response is expected 176112724Snikos.nikoleris@arm.com // make copy of current packet to forward, keep current 176212724Snikos.nikoleris@arm.com // copy for response handling 176312724Snikos.nikoleris@arm.com pkt = new Packet(tgt_pkt, false, true); 176412724Snikos.nikoleris@arm.com assert(!pkt->isWrite()); 176512724Snikos.nikoleris@arm.com } 176612724Snikos.nikoleris@arm.com 176712724Snikos.nikoleris@arm.com // play it safe and append (rather than set) the sender state, 176812724Snikos.nikoleris@arm.com // as forwarded packets may already have existing state 176912724Snikos.nikoleris@arm.com pkt->pushSenderState(mshr); 177012724Snikos.nikoleris@arm.com 177112724Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 177212724Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty block. Mark 177312724Snikos.nikoleris@arm.com // the packet so that the destination xbar can determine that 177412724Snikos.nikoleris@arm.com // there will be a follow-up write packet as well. 177512724Snikos.nikoleris@arm.com pkt->setSatisfied(); 177612724Snikos.nikoleris@arm.com } 177712724Snikos.nikoleris@arm.com 177812724Snikos.nikoleris@arm.com if (!memSidePort.sendTimingReq(pkt)) { 177912724Snikos.nikoleris@arm.com // we are awaiting a retry, but we 178012724Snikos.nikoleris@arm.com // delete the packet and will be creating a new packet 178112724Snikos.nikoleris@arm.com // when we get the opportunity 178212724Snikos.nikoleris@arm.com delete pkt; 178312724Snikos.nikoleris@arm.com 178412724Snikos.nikoleris@arm.com // note that we have now masked any requestBus and 178512724Snikos.nikoleris@arm.com // schedSendEvent (we will wait for a retry before 178612724Snikos.nikoleris@arm.com // doing anything), and this is so even if we do not 178712724Snikos.nikoleris@arm.com // care about this packet and might override it before 178812724Snikos.nikoleris@arm.com // it gets retried 178912724Snikos.nikoleris@arm.com return true; 179012724Snikos.nikoleris@arm.com } else { 179112724Snikos.nikoleris@arm.com // As part of the call to sendTimingReq the packet is 179212724Snikos.nikoleris@arm.com // forwarded to all neighbouring caches (and any caches 179312724Snikos.nikoleris@arm.com // above them) as a snoop. Thus at this point we know if 179412724Snikos.nikoleris@arm.com // any of the neighbouring caches are responding, and if 179512724Snikos.nikoleris@arm.com // so, we know it is dirty, and we can determine if it is 179612724Snikos.nikoleris@arm.com // being passed as Modified, making our MSHR the ordering 179712724Snikos.nikoleris@arm.com // point 179812724Snikos.nikoleris@arm.com bool pending_modified_resp = !pkt->hasSharers() && 179912724Snikos.nikoleris@arm.com pkt->cacheResponding(); 180012724Snikos.nikoleris@arm.com markInService(mshr, pending_modified_resp); 180112724Snikos.nikoleris@arm.com 180212724Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 180312724Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 180412724Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 180512724Snikos.nikoleris@arm.com // will update any copies to the path to the memory 180612724Snikos.nikoleris@arm.com // until the point of reference. 180712724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 180812724Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 180912724Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), 181012724Snikos.nikoleris@arm.com pkt->id); 181114035Sodanrc@yahoo.com.br PacketList writebacks; 181214035Sodanrc@yahoo.com.br writebacks.push_back(wb_pkt); 181314035Sodanrc@yahoo.com.br doWritebacks(writebacks, 0); 181412724Snikos.nikoleris@arm.com } 181512724Snikos.nikoleris@arm.com 181612724Snikos.nikoleris@arm.com return false; 181712724Snikos.nikoleris@arm.com } 181812724Snikos.nikoleris@arm.com} 181912724Snikos.nikoleris@arm.com 182012724Snikos.nikoleris@arm.combool 182112724Snikos.nikoleris@arm.comBaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 182212724Snikos.nikoleris@arm.com{ 182312724Snikos.nikoleris@arm.com assert(wq_entry); 182412724Snikos.nikoleris@arm.com 182512724Snikos.nikoleris@arm.com // always a single target for write queue entries 182612724Snikos.nikoleris@arm.com PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 182712724Snikos.nikoleris@arm.com 182812724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 182912724Snikos.nikoleris@arm.com 183012724Snikos.nikoleris@arm.com // forward as is, both for evictions and uncacheable writes 183112724Snikos.nikoleris@arm.com if (!memSidePort.sendTimingReq(tgt_pkt)) { 183212724Snikos.nikoleris@arm.com // note that we have now masked any requestBus and 183312724Snikos.nikoleris@arm.com // schedSendEvent (we will wait for a retry before 183412724Snikos.nikoleris@arm.com // doing anything), and this is so even if we do not 183512724Snikos.nikoleris@arm.com // care about this packet and might override it before 183612724Snikos.nikoleris@arm.com // it gets retried 183712724Snikos.nikoleris@arm.com return true; 183812724Snikos.nikoleris@arm.com } else { 183912724Snikos.nikoleris@arm.com markInService(wq_entry); 184012724Snikos.nikoleris@arm.com return false; 184112724Snikos.nikoleris@arm.com } 184212724Snikos.nikoleris@arm.com} 184312724Snikos.nikoleris@arm.com 184412724Snikos.nikoleris@arm.comvoid 184512724Snikos.nikoleris@arm.comBaseCache::serialize(CheckpointOut &cp) const 184612724Snikos.nikoleris@arm.com{ 184712724Snikos.nikoleris@arm.com bool dirty(isDirty()); 184812724Snikos.nikoleris@arm.com 184912724Snikos.nikoleris@arm.com if (dirty) { 185012724Snikos.nikoleris@arm.com warn("*** The cache still contains dirty data. ***\n"); 185112724Snikos.nikoleris@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 185212724Snikos.nikoleris@arm.com warn(" This checkpoint will not restore correctly " \ 185312724Snikos.nikoleris@arm.com "and dirty data in the cache will be lost!\n"); 185412724Snikos.nikoleris@arm.com } 185512724Snikos.nikoleris@arm.com 185612724Snikos.nikoleris@arm.com // Since we don't checkpoint the data in the cache, any dirty data 185712724Snikos.nikoleris@arm.com // will be lost when restoring from a checkpoint of a system that 185812724Snikos.nikoleris@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 185912724Snikos.nikoleris@arm.com // cache contains dirty data. 186012724Snikos.nikoleris@arm.com bool bad_checkpoint(dirty); 186112724Snikos.nikoleris@arm.com SERIALIZE_SCALAR(bad_checkpoint); 186212724Snikos.nikoleris@arm.com} 186312724Snikos.nikoleris@arm.com 186412724Snikos.nikoleris@arm.comvoid 186512724Snikos.nikoleris@arm.comBaseCache::unserialize(CheckpointIn &cp) 186612724Snikos.nikoleris@arm.com{ 186712724Snikos.nikoleris@arm.com bool bad_checkpoint; 186812724Snikos.nikoleris@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 186912724Snikos.nikoleris@arm.com if (bad_checkpoint) { 187012724Snikos.nikoleris@arm.com fatal("Restoring from checkpoints with dirty caches is not " 187112724Snikos.nikoleris@arm.com "supported in the classic memory system. Please remove any " 187212724Snikos.nikoleris@arm.com "caches or drain them properly before taking checkpoints.\n"); 187312724Snikos.nikoleris@arm.com } 187412724Snikos.nikoleris@arm.com} 187512724Snikos.nikoleris@arm.com 187612724Snikos.nikoleris@arm.comvoid 18772810SN/ABaseCache::regStats() 18782810SN/A{ 187913892Sgabeblack@google.com ClockedObject::regStats(); 188011522Sstephan.diestelhorst@arm.com 18812810SN/A using namespace Stats; 18822810SN/A 18832810SN/A // Hit statistics 18844022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 18854022SN/A MemCmd cmd(access_idx); 18864022SN/A const string &cstr = cmd.toString(); 18872810SN/A 18882810SN/A hits[access_idx] 18898833Sdam.sunwoo@arm.com .init(system->maxMasters()) 18902810SN/A .name(name() + "." + cstr + "_hits") 18912810SN/A .desc("number of " + cstr + " hits") 18922810SN/A .flags(total | nozero | nonan) 18932810SN/A ; 18948833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18958833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 18968833Sdam.sunwoo@arm.com } 18972810SN/A } 18982810SN/A 18994871SN/A// These macros make it easier to sum the right subset of commands and 19004871SN/A// to change the subset of commands that are considered "demand" vs 19014871SN/A// "non-demand" 19024871SN/A#define SUM_DEMAND(s) \ 190311455Sandreas.hansson@arm.com (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \ 190410885Sandreas.hansson@arm.com s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 19054871SN/A 19064871SN/A// should writebacks be included here? prior code was inconsistent... 19074871SN/A#define SUM_NON_DEMAND(s) \ 190813367Syuetsu.kodama@riken.jp (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq] + s[MemCmd::SoftPFExReq]) 19094871SN/A 19102810SN/A demandHits 19112810SN/A .name(name() + ".demand_hits") 19122810SN/A .desc("number of demand (read+write) hits") 19138833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19142810SN/A ; 19154871SN/A demandHits = SUM_DEMAND(hits); 19168833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19178833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 19188833Sdam.sunwoo@arm.com } 19192810SN/A 19202810SN/A overallHits 19212810SN/A .name(name() + ".overall_hits") 19222810SN/A .desc("number of overall hits") 19238833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19242810SN/A ; 19254871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 19268833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19278833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 19288833Sdam.sunwoo@arm.com } 19292810SN/A 19302810SN/A // Miss statistics 19314022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 19324022SN/A MemCmd cmd(access_idx); 19334022SN/A const string &cstr = cmd.toString(); 19342810SN/A 19352810SN/A misses[access_idx] 19368833Sdam.sunwoo@arm.com .init(system->maxMasters()) 19372810SN/A .name(name() + "." + cstr + "_misses") 19382810SN/A .desc("number of " + cstr + " misses") 19392810SN/A .flags(total | nozero | nonan) 19402810SN/A ; 19418833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19428833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 19438833Sdam.sunwoo@arm.com } 19442810SN/A } 19452810SN/A 19462810SN/A demandMisses 19472810SN/A .name(name() + ".demand_misses") 19482810SN/A .desc("number of demand (read+write) misses") 19498833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19502810SN/A ; 19514871SN/A demandMisses = SUM_DEMAND(misses); 19528833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19538833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 19548833Sdam.sunwoo@arm.com } 19552810SN/A 19562810SN/A overallMisses 19572810SN/A .name(name() + ".overall_misses") 19582810SN/A .desc("number of overall misses") 19598833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19602810SN/A ; 19614871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 19628833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19638833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 19648833Sdam.sunwoo@arm.com } 19652810SN/A 19662810SN/A // Miss latency statistics 19674022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 19684022SN/A MemCmd cmd(access_idx); 19694022SN/A const string &cstr = cmd.toString(); 19702810SN/A 19712810SN/A missLatency[access_idx] 19728833Sdam.sunwoo@arm.com .init(system->maxMasters()) 19732810SN/A .name(name() + "." + cstr + "_miss_latency") 19742810SN/A .desc("number of " + cstr + " miss cycles") 19752810SN/A .flags(total | nozero | nonan) 19762810SN/A ; 19778833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19788833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 19798833Sdam.sunwoo@arm.com } 19802810SN/A } 19812810SN/A 19822810SN/A demandMissLatency 19832810SN/A .name(name() + ".demand_miss_latency") 19842810SN/A .desc("number of demand (read+write) miss cycles") 19858833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19862810SN/A ; 19874871SN/A demandMissLatency = SUM_DEMAND(missLatency); 19888833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19898833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 19908833Sdam.sunwoo@arm.com } 19912810SN/A 19922810SN/A overallMissLatency 19932810SN/A .name(name() + ".overall_miss_latency") 19942810SN/A .desc("number of overall miss cycles") 19958833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19962810SN/A ; 19974871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 19988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19998833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 20008833Sdam.sunwoo@arm.com } 20012810SN/A 20022810SN/A // access formulas 20034022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 20044022SN/A MemCmd cmd(access_idx); 20054022SN/A const string &cstr = cmd.toString(); 20062810SN/A 20072810SN/A accesses[access_idx] 20082810SN/A .name(name() + "." + cstr + "_accesses") 20092810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 20102810SN/A .flags(total | nozero | nonan) 20112810SN/A ; 20128833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 20132810SN/A 20148833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20158833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 20168833Sdam.sunwoo@arm.com } 20172810SN/A } 20182810SN/A 20192810SN/A demandAccesses 20202810SN/A .name(name() + ".demand_accesses") 20212810SN/A .desc("number of demand (read+write) accesses") 20228833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20232810SN/A ; 20242810SN/A demandAccesses = demandHits + demandMisses; 20258833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20268833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 20278833Sdam.sunwoo@arm.com } 20282810SN/A 20292810SN/A overallAccesses 20302810SN/A .name(name() + ".overall_accesses") 20312810SN/A .desc("number of overall (read+write) accesses") 20328833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20332810SN/A ; 20342810SN/A overallAccesses = overallHits + overallMisses; 20358833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20368833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 20378833Sdam.sunwoo@arm.com } 20382810SN/A 20392810SN/A // miss rate formulas 20404022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 20414022SN/A MemCmd cmd(access_idx); 20424022SN/A const string &cstr = cmd.toString(); 20432810SN/A 20442810SN/A missRate[access_idx] 20452810SN/A .name(name() + "." + cstr + "_miss_rate") 20462810SN/A .desc("miss rate for " + cstr + " accesses") 20472810SN/A .flags(total | nozero | nonan) 20482810SN/A ; 20498833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 20502810SN/A 20518833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20528833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 20538833Sdam.sunwoo@arm.com } 20542810SN/A } 20552810SN/A 20562810SN/A demandMissRate 20572810SN/A .name(name() + ".demand_miss_rate") 20582810SN/A .desc("miss rate for demand accesses") 20598833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20602810SN/A ; 20612810SN/A demandMissRate = demandMisses / demandAccesses; 20628833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20638833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 20648833Sdam.sunwoo@arm.com } 20652810SN/A 20662810SN/A overallMissRate 20672810SN/A .name(name() + ".overall_miss_rate") 20682810SN/A .desc("miss rate for overall accesses") 20698833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20702810SN/A ; 20712810SN/A overallMissRate = overallMisses / overallAccesses; 20728833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20738833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 20748833Sdam.sunwoo@arm.com } 20752810SN/A 20762810SN/A // miss latency formulas 20774022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 20784022SN/A MemCmd cmd(access_idx); 20794022SN/A const string &cstr = cmd.toString(); 20802810SN/A 20812810SN/A avgMissLatency[access_idx] 20822810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 20832810SN/A .desc("average " + cstr + " miss latency") 20842810SN/A .flags(total | nozero | nonan) 20852810SN/A ; 20862810SN/A avgMissLatency[access_idx] = 20872810SN/A missLatency[access_idx] / misses[access_idx]; 20888833Sdam.sunwoo@arm.com 20898833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20908833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 20918833Sdam.sunwoo@arm.com } 20922810SN/A } 20932810SN/A 20942810SN/A demandAvgMissLatency 20952810SN/A .name(name() + ".demand_avg_miss_latency") 20962810SN/A .desc("average overall miss latency") 20978833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20982810SN/A ; 20992810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 21008833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21018833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 21028833Sdam.sunwoo@arm.com } 21032810SN/A 21042810SN/A overallAvgMissLatency 21052810SN/A .name(name() + ".overall_avg_miss_latency") 21062810SN/A .desc("average overall miss latency") 21078833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21082810SN/A ; 21092810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 21108833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21118833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 21128833Sdam.sunwoo@arm.com } 21132810SN/A 21142810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 21152810SN/A blocked_cycles 21162810SN/A .name(name() + ".blocked_cycles") 21172810SN/A .desc("number of cycles access was blocked") 21182810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 21192810SN/A .subname(Blocked_NoTargets, "no_targets") 21202810SN/A ; 21212810SN/A 21222810SN/A 21232810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 21242810SN/A blocked_causes 21252810SN/A .name(name() + ".blocked") 21262810SN/A .desc("number of cycles access was blocked") 21272810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 21282810SN/A .subname(Blocked_NoTargets, "no_targets") 21292810SN/A ; 21302810SN/A 21312810SN/A avg_blocked 21322810SN/A .name(name() + ".avg_blocked_cycles") 21332810SN/A .desc("average number of cycles each access was blocked") 21342810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 21352810SN/A .subname(Blocked_NoTargets, "no_targets") 21362810SN/A ; 21372810SN/A 21382810SN/A avg_blocked = blocked_cycles / blocked_causes; 21392810SN/A 214011436SRekai.GonzalezAlberquilla@arm.com unusedPrefetches 214111436SRekai.GonzalezAlberquilla@arm.com .name(name() + ".unused_prefetches") 214211436SRekai.GonzalezAlberquilla@arm.com .desc("number of HardPF blocks evicted w/o reference") 214311436SRekai.GonzalezAlberquilla@arm.com .flags(nozero) 214411436SRekai.GonzalezAlberquilla@arm.com ; 214511436SRekai.GonzalezAlberquilla@arm.com 21464626SN/A writebacks 21478833Sdam.sunwoo@arm.com .init(system->maxMasters()) 21484626SN/A .name(name() + ".writebacks") 21494626SN/A .desc("number of writebacks") 21508833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21514626SN/A ; 21528833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21538833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 21548833Sdam.sunwoo@arm.com } 21554626SN/A 21564626SN/A // MSHR statistics 21574626SN/A // MSHR hit statistics 21584626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 21594626SN/A MemCmd cmd(access_idx); 21604626SN/A const string &cstr = cmd.toString(); 21614626SN/A 21624626SN/A mshr_hits[access_idx] 21638833Sdam.sunwoo@arm.com .init(system->maxMasters()) 21644626SN/A .name(name() + "." + cstr + "_mshr_hits") 21654626SN/A .desc("number of " + cstr + " MSHR hits") 21664626SN/A .flags(total | nozero | nonan) 21674626SN/A ; 21688833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21698833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 21708833Sdam.sunwoo@arm.com } 21714626SN/A } 21724626SN/A 21734626SN/A demandMshrHits 21744626SN/A .name(name() + ".demand_mshr_hits") 21754626SN/A .desc("number of demand (read+write) MSHR hits") 21768833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21774626SN/A ; 21784871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 21798833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21808833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 21818833Sdam.sunwoo@arm.com } 21824626SN/A 21834626SN/A overallMshrHits 21844626SN/A .name(name() + ".overall_mshr_hits") 21854626SN/A .desc("number of overall MSHR hits") 21868833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21874626SN/A ; 21884871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 21898833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21908833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 21918833Sdam.sunwoo@arm.com } 21924626SN/A 21934626SN/A // MSHR miss statistics 21944626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 21954626SN/A MemCmd cmd(access_idx); 21964626SN/A const string &cstr = cmd.toString(); 21974626SN/A 21984626SN/A mshr_misses[access_idx] 21998833Sdam.sunwoo@arm.com .init(system->maxMasters()) 22004626SN/A .name(name() + "." + cstr + "_mshr_misses") 22014626SN/A .desc("number of " + cstr + " MSHR misses") 22024626SN/A .flags(total | nozero | nonan) 22034626SN/A ; 22048833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 22058833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 22068833Sdam.sunwoo@arm.com } 22074626SN/A } 22084626SN/A 22094626SN/A demandMshrMisses 22104626SN/A .name(name() + ".demand_mshr_misses") 22114626SN/A .desc("number of demand (read+write) MSHR misses") 22128833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 22134626SN/A ; 22144871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 22158833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 22168833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 22178833Sdam.sunwoo@arm.com } 22184626SN/A 22194626SN/A overallMshrMisses 22204626SN/A .name(name() + ".overall_mshr_misses") 22214626SN/A .desc("number of overall MSHR misses") 22228833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 22234626SN/A ; 22244871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 22258833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 22268833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 22278833Sdam.sunwoo@arm.com } 22284626SN/A 22294626SN/A // MSHR miss latency statistics 22304626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 22314626SN/A MemCmd cmd(access_idx); 22324626SN/A const string &cstr = cmd.toString(); 22334626SN/A 22344626SN/A mshr_miss_latency[access_idx] 22358833Sdam.sunwoo@arm.com .init(system->maxMasters()) 22364626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 22374626SN/A .desc("number of " + cstr + " MSHR miss cycles") 22384626SN/A .flags(total | nozero | nonan) 22394626SN/A ; 22408833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 22418833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 22428833Sdam.sunwoo@arm.com } 22434626SN/A } 22444626SN/A 22454626SN/A demandMshrMissLatency 22464626SN/A .name(name() + ".demand_mshr_miss_latency") 22474626SN/A .desc("number of demand (read+write) MSHR miss cycles") 22488833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 22494626SN/A ; 22504871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 22518833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 22528833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 22538833Sdam.sunwoo@arm.com } 22544626SN/A 22554626SN/A overallMshrMissLatency 22564626SN/A .name(name() + ".overall_mshr_miss_latency") 22574626SN/A .desc("number of overall MSHR miss cycles") 22588833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 22594626SN/A ; 22604871SN/A overallMshrMissLatency = 22614871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 22628833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 22638833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 22648833Sdam.sunwoo@arm.com } 22654626SN/A 22664626SN/A // MSHR uncacheable statistics 22674626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 22684626SN/A MemCmd cmd(access_idx); 22694626SN/A const string &cstr = cmd.toString(); 22704626SN/A 22714626SN/A mshr_uncacheable[access_idx] 22728833Sdam.sunwoo@arm.com .init(system->maxMasters()) 22734626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 22744626SN/A .desc("number of " + cstr + " MSHR uncacheable") 22754626SN/A .flags(total | nozero | nonan) 22764626SN/A ; 22778833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 22788833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 22798833Sdam.sunwoo@arm.com } 22804626SN/A } 22814626SN/A 22824626SN/A overallMshrUncacheable 22834626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 22844626SN/A .desc("number of overall MSHR uncacheable misses") 22858833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 22864626SN/A ; 22874871SN/A overallMshrUncacheable = 22884871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 22898833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 22908833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 22918833Sdam.sunwoo@arm.com } 22924626SN/A 22934626SN/A // MSHR miss latency statistics 22944626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 22954626SN/A MemCmd cmd(access_idx); 22964626SN/A const string &cstr = cmd.toString(); 22974626SN/A 22984626SN/A mshr_uncacheable_lat[access_idx] 22998833Sdam.sunwoo@arm.com .init(system->maxMasters()) 23004626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 23014626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 23024626SN/A .flags(total | nozero | nonan) 23034626SN/A ; 23048833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 230511483Snikos.nikoleris@arm.com mshr_uncacheable_lat[access_idx].subname( 230611483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 23078833Sdam.sunwoo@arm.com } 23084626SN/A } 23094626SN/A 23104626SN/A overallMshrUncacheableLatency 23114626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 23124626SN/A .desc("number of overall MSHR uncacheable cycles") 23138833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 23144626SN/A ; 23154871SN/A overallMshrUncacheableLatency = 23164871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 23174871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 23188833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 23198833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 23208833Sdam.sunwoo@arm.com } 23214626SN/A 23224626SN/A // MSHR miss rate formulas 23234626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 23244626SN/A MemCmd cmd(access_idx); 23254626SN/A const string &cstr = cmd.toString(); 23264626SN/A 23274626SN/A mshrMissRate[access_idx] 23284626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 23294626SN/A .desc("mshr miss rate for " + cstr + " accesses") 23304626SN/A .flags(total | nozero | nonan) 23314626SN/A ; 23324626SN/A mshrMissRate[access_idx] = 23334626SN/A mshr_misses[access_idx] / accesses[access_idx]; 23348833Sdam.sunwoo@arm.com 23358833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 23368833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 23378833Sdam.sunwoo@arm.com } 23384626SN/A } 23394626SN/A 23404626SN/A demandMshrMissRate 23414626SN/A .name(name() + ".demand_mshr_miss_rate") 23424626SN/A .desc("mshr miss rate for demand accesses") 23438833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 23444626SN/A ; 23454626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 23468833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 23478833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 23488833Sdam.sunwoo@arm.com } 23494626SN/A 23504626SN/A overallMshrMissRate 23514626SN/A .name(name() + ".overall_mshr_miss_rate") 23524626SN/A .desc("mshr miss rate for overall accesses") 23538833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 23544626SN/A ; 23554626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 23568833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 23578833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 23588833Sdam.sunwoo@arm.com } 23594626SN/A 23604626SN/A // mshrMiss latency formulas 23614626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 23624626SN/A MemCmd cmd(access_idx); 23634626SN/A const string &cstr = cmd.toString(); 23644626SN/A 23654626SN/A avgMshrMissLatency[access_idx] 23664626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 23674626SN/A .desc("average " + cstr + " mshr miss latency") 23684626SN/A .flags(total | nozero | nonan) 23694626SN/A ; 23704626SN/A avgMshrMissLatency[access_idx] = 23714626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 23728833Sdam.sunwoo@arm.com 23738833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 237411483Snikos.nikoleris@arm.com avgMshrMissLatency[access_idx].subname( 237511483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 23768833Sdam.sunwoo@arm.com } 23774626SN/A } 23784626SN/A 23794626SN/A demandAvgMshrMissLatency 23804626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 23814626SN/A .desc("average overall mshr miss latency") 23828833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 23834626SN/A ; 23844626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 23858833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 23868833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 23878833Sdam.sunwoo@arm.com } 23884626SN/A 23894626SN/A overallAvgMshrMissLatency 23904626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 23914626SN/A .desc("average overall mshr miss latency") 23928833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 23934626SN/A ; 23944626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 23958833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 23968833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 23978833Sdam.sunwoo@arm.com } 23984626SN/A 23994626SN/A // mshrUncacheable latency formulas 24004626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 24014626SN/A MemCmd cmd(access_idx); 24024626SN/A const string &cstr = cmd.toString(); 24034626SN/A 24044626SN/A avgMshrUncacheableLatency[access_idx] 24054626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 24064626SN/A .desc("average " + cstr + " mshr uncacheable latency") 24074626SN/A .flags(total | nozero | nonan) 24084626SN/A ; 24094626SN/A avgMshrUncacheableLatency[access_idx] = 24104626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 24118833Sdam.sunwoo@arm.com 24128833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 241311483Snikos.nikoleris@arm.com avgMshrUncacheableLatency[access_idx].subname( 241411483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 24158833Sdam.sunwoo@arm.com } 24164626SN/A } 24174626SN/A 24184626SN/A overallAvgMshrUncacheableLatency 24194626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 24204626SN/A .desc("average overall mshr uncacheable latency") 24218833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 24224626SN/A ; 242311483Snikos.nikoleris@arm.com overallAvgMshrUncacheableLatency = 242411483Snikos.nikoleris@arm.com overallMshrUncacheableLatency / overallMshrUncacheable; 24258833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 24268833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 24278833Sdam.sunwoo@arm.com } 24284626SN/A 242912702Snikos.nikoleris@arm.com replacements 243012702Snikos.nikoleris@arm.com .name(name() + ".replacements") 243112702Snikos.nikoleris@arm.com .desc("number of replacements") 243212702Snikos.nikoleris@arm.com ; 243313947Sodanrc@yahoo.com.br 243413947Sodanrc@yahoo.com.br dataExpansions 243513947Sodanrc@yahoo.com.br .name(name() + ".data_expansions") 243613947Sodanrc@yahoo.com.br .desc("number of data expansions") 243713947Sodanrc@yahoo.com.br .flags(nozero | nonan) 243813947Sodanrc@yahoo.com.br ; 24392810SN/A} 244012724Snikos.nikoleris@arm.com 244113416Sjavier.bueno@metempsy.comvoid 244213416Sjavier.bueno@metempsy.comBaseCache::regProbePoints() 244313416Sjavier.bueno@metempsy.com{ 244413416Sjavier.bueno@metempsy.com ppHit = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Hit"); 244513416Sjavier.bueno@metempsy.com ppMiss = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Miss"); 244613717Sivan.pizarro@metempsy.com ppFill = new ProbePointArg<PacketPtr>(this->getProbeManager(), "Fill"); 244713416Sjavier.bueno@metempsy.com} 244813416Sjavier.bueno@metempsy.com 244912724Snikos.nikoleris@arm.com/////////////// 245012724Snikos.nikoleris@arm.com// 245112724Snikos.nikoleris@arm.com// CpuSidePort 245212724Snikos.nikoleris@arm.com// 245312724Snikos.nikoleris@arm.com/////////////// 245412724Snikos.nikoleris@arm.combool 245512724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 245612724Snikos.nikoleris@arm.com{ 245712725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 245812725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 245912725Snikos.nikoleris@arm.com 246012725Snikos.nikoleris@arm.com assert(pkt->isResponse()); 246112725Snikos.nikoleris@arm.com 246212724Snikos.nikoleris@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 246312724Snikos.nikoleris@arm.com cache->recvTimingSnoopResp(pkt); 246412724Snikos.nikoleris@arm.com return true; 246512724Snikos.nikoleris@arm.com} 246612724Snikos.nikoleris@arm.com 246712724Snikos.nikoleris@arm.com 246812724Snikos.nikoleris@arm.combool 246912724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::tryTiming(PacketPtr pkt) 247012724Snikos.nikoleris@arm.com{ 247112725Snikos.nikoleris@arm.com if (cache->system->bypassCaches() || pkt->isExpressSnoop()) { 247212724Snikos.nikoleris@arm.com // always let express snoop packets through even if blocked 247312724Snikos.nikoleris@arm.com return true; 247412724Snikos.nikoleris@arm.com } else if (blocked || mustSendRetry) { 247512724Snikos.nikoleris@arm.com // either already committed to send a retry, or blocked 247612724Snikos.nikoleris@arm.com mustSendRetry = true; 247712724Snikos.nikoleris@arm.com return false; 247812724Snikos.nikoleris@arm.com } 247912724Snikos.nikoleris@arm.com mustSendRetry = false; 248012724Snikos.nikoleris@arm.com return true; 248112724Snikos.nikoleris@arm.com} 248212724Snikos.nikoleris@arm.com 248312724Snikos.nikoleris@arm.combool 248412724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 248512724Snikos.nikoleris@arm.com{ 248612725Snikos.nikoleris@arm.com assert(pkt->isRequest()); 248712725Snikos.nikoleris@arm.com 248812725Snikos.nikoleris@arm.com if (cache->system->bypassCaches()) { 248912725Snikos.nikoleris@arm.com // Just forward the packet if caches are disabled. 249012725Snikos.nikoleris@arm.com // @todo This should really enqueue the packet rather 249112725Snikos.nikoleris@arm.com bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt); 249212725Snikos.nikoleris@arm.com assert(success); 249312725Snikos.nikoleris@arm.com return true; 249412725Snikos.nikoleris@arm.com } else if (tryTiming(pkt)) { 249512724Snikos.nikoleris@arm.com cache->recvTimingReq(pkt); 249612724Snikos.nikoleris@arm.com return true; 249712724Snikos.nikoleris@arm.com } 249812724Snikos.nikoleris@arm.com return false; 249912724Snikos.nikoleris@arm.com} 250012724Snikos.nikoleris@arm.com 250112724Snikos.nikoleris@arm.comTick 250212724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvAtomic(PacketPtr pkt) 250312724Snikos.nikoleris@arm.com{ 250412725Snikos.nikoleris@arm.com if (cache->system->bypassCaches()) { 250512725Snikos.nikoleris@arm.com // Forward the request if the system is in cache bypass mode. 250612725Snikos.nikoleris@arm.com return cache->memSidePort.sendAtomic(pkt); 250712725Snikos.nikoleris@arm.com } else { 250812725Snikos.nikoleris@arm.com return cache->recvAtomic(pkt); 250912725Snikos.nikoleris@arm.com } 251012724Snikos.nikoleris@arm.com} 251112724Snikos.nikoleris@arm.com 251212724Snikos.nikoleris@arm.comvoid 251312724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvFunctional(PacketPtr pkt) 251412724Snikos.nikoleris@arm.com{ 251512725Snikos.nikoleris@arm.com if (cache->system->bypassCaches()) { 251612725Snikos.nikoleris@arm.com // The cache should be flushed if we are in cache bypass mode, 251712725Snikos.nikoleris@arm.com // so we don't need to check if we need to update anything. 251812725Snikos.nikoleris@arm.com cache->memSidePort.sendFunctional(pkt); 251912725Snikos.nikoleris@arm.com return; 252012725Snikos.nikoleris@arm.com } 252112725Snikos.nikoleris@arm.com 252212724Snikos.nikoleris@arm.com // functional request 252312724Snikos.nikoleris@arm.com cache->functionalAccess(pkt, true); 252412724Snikos.nikoleris@arm.com} 252512724Snikos.nikoleris@arm.com 252612724Snikos.nikoleris@arm.comAddrRangeList 252712724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::getAddrRanges() const 252812724Snikos.nikoleris@arm.com{ 252912724Snikos.nikoleris@arm.com return cache->getAddrRanges(); 253012724Snikos.nikoleris@arm.com} 253112724Snikos.nikoleris@arm.com 253212724Snikos.nikoleris@arm.com 253312724Snikos.nikoleris@arm.comBaseCache:: 253412724Snikos.nikoleris@arm.comCpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache, 253512724Snikos.nikoleris@arm.com const std::string &_label) 253612724Snikos.nikoleris@arm.com : CacheSlavePort(_name, _cache, _label), cache(_cache) 253712724Snikos.nikoleris@arm.com{ 253812724Snikos.nikoleris@arm.com} 253912724Snikos.nikoleris@arm.com 254012724Snikos.nikoleris@arm.com/////////////// 254112724Snikos.nikoleris@arm.com// 254212724Snikos.nikoleris@arm.com// MemSidePort 254312724Snikos.nikoleris@arm.com// 254412724Snikos.nikoleris@arm.com/////////////// 254512724Snikos.nikoleris@arm.combool 254612724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvTimingResp(PacketPtr pkt) 254712724Snikos.nikoleris@arm.com{ 254812724Snikos.nikoleris@arm.com cache->recvTimingResp(pkt); 254912724Snikos.nikoleris@arm.com return true; 255012724Snikos.nikoleris@arm.com} 255112724Snikos.nikoleris@arm.com 255212724Snikos.nikoleris@arm.com// Express snooping requests to memside port 255312724Snikos.nikoleris@arm.comvoid 255412724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 255512724Snikos.nikoleris@arm.com{ 255612725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 255712725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 255812725Snikos.nikoleris@arm.com 255912724Snikos.nikoleris@arm.com // handle snooping requests 256012724Snikos.nikoleris@arm.com cache->recvTimingSnoopReq(pkt); 256112724Snikos.nikoleris@arm.com} 256212724Snikos.nikoleris@arm.com 256312724Snikos.nikoleris@arm.comTick 256412724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 256512724Snikos.nikoleris@arm.com{ 256612725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 256712725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 256812725Snikos.nikoleris@arm.com 256912724Snikos.nikoleris@arm.com return cache->recvAtomicSnoop(pkt); 257012724Snikos.nikoleris@arm.com} 257112724Snikos.nikoleris@arm.com 257212724Snikos.nikoleris@arm.comvoid 257312724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 257412724Snikos.nikoleris@arm.com{ 257512725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 257612725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 257712725Snikos.nikoleris@arm.com 257812724Snikos.nikoleris@arm.com // functional snoop (note that in contrast to atomic we don't have 257912724Snikos.nikoleris@arm.com // a specific functionalSnoop method, as they have the same 258012724Snikos.nikoleris@arm.com // behaviour regardless) 258112724Snikos.nikoleris@arm.com cache->functionalAccess(pkt, false); 258212724Snikos.nikoleris@arm.com} 258312724Snikos.nikoleris@arm.com 258412724Snikos.nikoleris@arm.comvoid 258512724Snikos.nikoleris@arm.comBaseCache::CacheReqPacketQueue::sendDeferredPacket() 258612724Snikos.nikoleris@arm.com{ 258712724Snikos.nikoleris@arm.com // sanity check 258812724Snikos.nikoleris@arm.com assert(!waitingOnRetry); 258912724Snikos.nikoleris@arm.com 259012724Snikos.nikoleris@arm.com // there should never be any deferred request packets in the 259112724Snikos.nikoleris@arm.com // queue, instead we resly on the cache to provide the packets 259212724Snikos.nikoleris@arm.com // from the MSHR queue or write queue 259312724Snikos.nikoleris@arm.com assert(deferredPacketReadyTime() == MaxTick); 259412724Snikos.nikoleris@arm.com 259512724Snikos.nikoleris@arm.com // check for request packets (requests & writebacks) 259612724Snikos.nikoleris@arm.com QueueEntry* entry = cache.getNextQueueEntry(); 259712724Snikos.nikoleris@arm.com 259812724Snikos.nikoleris@arm.com if (!entry) { 259912724Snikos.nikoleris@arm.com // can happen if e.g. we attempt a writeback and fail, but 260012724Snikos.nikoleris@arm.com // before the retry, the writeback is eliminated because 260112724Snikos.nikoleris@arm.com // we snoop another cache's ReadEx. 260212724Snikos.nikoleris@arm.com } else { 260312724Snikos.nikoleris@arm.com // let our snoop responses go first if there are responses to 260412724Snikos.nikoleris@arm.com // the same addresses 260513860Sodanrc@yahoo.com.br if (checkConflictingSnoop(entry->getTarget()->pkt)) { 260612724Snikos.nikoleris@arm.com return; 260712724Snikos.nikoleris@arm.com } 260812724Snikos.nikoleris@arm.com waitingOnRetry = entry->sendPacket(cache); 260912724Snikos.nikoleris@arm.com } 261012724Snikos.nikoleris@arm.com 261112724Snikos.nikoleris@arm.com // if we succeeded and are not waiting for a retry, schedule the 261212724Snikos.nikoleris@arm.com // next send considering when the next queue is ready, note that 261312724Snikos.nikoleris@arm.com // snoop responses have their own packet queue and thus schedule 261412724Snikos.nikoleris@arm.com // their own events 261512724Snikos.nikoleris@arm.com if (!waitingOnRetry) { 261612724Snikos.nikoleris@arm.com schedSendEvent(cache.nextQueueReadyTime()); 261712724Snikos.nikoleris@arm.com } 261812724Snikos.nikoleris@arm.com} 261912724Snikos.nikoleris@arm.com 262012724Snikos.nikoleris@arm.comBaseCache::MemSidePort::MemSidePort(const std::string &_name, 262112724Snikos.nikoleris@arm.com BaseCache *_cache, 262212724Snikos.nikoleris@arm.com const std::string &_label) 262312724Snikos.nikoleris@arm.com : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 262412724Snikos.nikoleris@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 262513564Snikos.nikoleris@arm.com _snoopRespQueue(*_cache, *this, true, _label), cache(_cache) 262612724Snikos.nikoleris@arm.com{ 262712724Snikos.nikoleris@arm.com} 262813352Snikos.nikoleris@arm.com 262913352Snikos.nikoleris@arm.comvoid 263013352Snikos.nikoleris@arm.comWriteAllocator::updateMode(Addr write_addr, unsigned write_size, 263113352Snikos.nikoleris@arm.com Addr blk_addr) 263213352Snikos.nikoleris@arm.com{ 263313352Snikos.nikoleris@arm.com // check if we are continuing where the last write ended 263413352Snikos.nikoleris@arm.com if (nextAddr == write_addr) { 263513352Snikos.nikoleris@arm.com delayCtr[blk_addr] = delayThreshold; 263613352Snikos.nikoleris@arm.com // stop if we have already saturated 263713352Snikos.nikoleris@arm.com if (mode != WriteMode::NO_ALLOCATE) { 263813352Snikos.nikoleris@arm.com byteCount += write_size; 263913352Snikos.nikoleris@arm.com // switch to streaming mode if we have passed the lower 264013352Snikos.nikoleris@arm.com // threshold 264113352Snikos.nikoleris@arm.com if (mode == WriteMode::ALLOCATE && 264213352Snikos.nikoleris@arm.com byteCount > coalesceLimit) { 264313352Snikos.nikoleris@arm.com mode = WriteMode::COALESCE; 264413352Snikos.nikoleris@arm.com DPRINTF(Cache, "Switched to write coalescing\n"); 264513352Snikos.nikoleris@arm.com } else if (mode == WriteMode::COALESCE && 264613352Snikos.nikoleris@arm.com byteCount > noAllocateLimit) { 264713352Snikos.nikoleris@arm.com // and continue and switch to non-allocating mode if we 264813352Snikos.nikoleris@arm.com // pass the upper threshold 264913352Snikos.nikoleris@arm.com mode = WriteMode::NO_ALLOCATE; 265013352Snikos.nikoleris@arm.com DPRINTF(Cache, "Switched to write-no-allocate\n"); 265113352Snikos.nikoleris@arm.com } 265213352Snikos.nikoleris@arm.com } 265313352Snikos.nikoleris@arm.com } else { 265413352Snikos.nikoleris@arm.com // we did not see a write matching the previous one, start 265513352Snikos.nikoleris@arm.com // over again 265613352Snikos.nikoleris@arm.com byteCount = write_size; 265713352Snikos.nikoleris@arm.com mode = WriteMode::ALLOCATE; 265813352Snikos.nikoleris@arm.com resetDelay(blk_addr); 265913352Snikos.nikoleris@arm.com } 266013352Snikos.nikoleris@arm.com nextAddr = write_addr + write_size; 266113352Snikos.nikoleris@arm.com} 266213352Snikos.nikoleris@arm.com 266313352Snikos.nikoleris@arm.comWriteAllocator* 266413352Snikos.nikoleris@arm.comWriteAllocatorParams::create() 266513352Snikos.nikoleris@arm.com{ 266613352Snikos.nikoleris@arm.com return new WriteAllocator(this); 266713352Snikos.nikoleris@arm.com} 2668