1# Copyright (c) 2012 The Regents of The University of Michigan
2# Copyright (c) 2016 Centre National de la Recherche Scientifique
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Ron Dreslinski
29#          Anastasiia Butko
30#          Louisa Bessad
31
32from __future__ import print_function
33from __future__ import absolute_import
34
35from m5.objects import *
36
37#-----------------------------------------------------------------------
38#                ex5 big core (based on the ARM Cortex-A15)
39#-----------------------------------------------------------------------
40
41# Simple ALU Instructions have a latency of 1
42class ex5_big_Simple_Int(FUDesc):
43    opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
44    count = 2
45
46# Complex ALU instructions have a variable latencies
47class ex5_big_Complex_Int(FUDesc):
48    opList = [ OpDesc(opClass='IntMult', opLat=4, pipelined=True),
49               OpDesc(opClass='IntDiv', opLat=11, pipelined=False),
50               OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
51    count = 1
52
53# Floating point and SIMD instructions
54class ex5_big_FP(FUDesc):
55    opList = [ OpDesc(opClass='SimdAdd', opLat=3),
56               OpDesc(opClass='SimdAddAcc', opLat=4),
57               OpDesc(opClass='SimdAlu', opLat=4),
58               OpDesc(opClass='SimdCmp', opLat=4),
59               OpDesc(opClass='SimdCvt', opLat=3),
60               OpDesc(opClass='SimdMisc', opLat=3),
61               OpDesc(opClass='SimdMult',opLat=6),
62               OpDesc(opClass='SimdMultAcc',opLat=5),
63               OpDesc(opClass='SimdShift',opLat=3),
64               OpDesc(opClass='SimdShiftAcc', opLat=3),
65               OpDesc(opClass='SimdSqrt', opLat=9),
66               OpDesc(opClass='SimdFloatAdd',opLat=6),
67               OpDesc(opClass='SimdFloatAlu',opLat=5),
68               OpDesc(opClass='SimdFloatCmp', opLat=3),
69               OpDesc(opClass='SimdFloatCvt', opLat=3),
70               OpDesc(opClass='SimdFloatDiv', opLat=21),
71               OpDesc(opClass='SimdFloatMisc', opLat=3),
72               OpDesc(opClass='SimdFloatMult', opLat=6),
73               OpDesc(opClass='SimdFloatMultAcc',opLat=1),
74               OpDesc(opClass='SimdFloatSqrt', opLat=9),
75               OpDesc(opClass='FloatAdd', opLat=6),
76               OpDesc(opClass='FloatCmp', opLat=5),
77               OpDesc(opClass='FloatCvt', opLat=5),
78               OpDesc(opClass='FloatDiv', opLat=12, pipelined=False),
79               OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
80               OpDesc(opClass='FloatMult', opLat=8) ]
81    count = 2
82
83
84# Load/Store Units
85class ex5_big_Load(FUDesc):
86    opList = [ OpDesc(opClass='MemRead',opLat=2) ]
87    count = 1
88
89class ex5_big_Store(FUDesc):
90    opList = [OpDesc(opClass='MemWrite',opLat=2) ]
91    count = 1
92
93# Functional Units for this CPU
94class ex5_big_FUP(FUPool):
95    FUList = [ex5_big_Simple_Int(), ex5_big_Complex_Int(),
96              ex5_big_Load(), ex5_big_Store(), ex5_big_FP()]
97
98# Bi-Mode Branch Predictor
99class ex5_big_BP(BiModeBP):
100    globalPredictorSize = 4096
101    globalCtrBits = 2
102    choicePredictorSize = 1024
103    choiceCtrBits = 3
104    BTBEntries = 4096
105    BTBTagSize = 18
106    RASSize = 48
107    instShiftAmt = 2
108
109class ex5_big(DerivO3CPU):
110    LQEntries = 16
111    SQEntries = 16
112    LSQDepCheckShift = 0
113    LFSTSize = 1024
114    SSITSize = 1024
115    decodeToFetchDelay = 1
116    renameToFetchDelay = 1
117    iewToFetchDelay = 1
118    commitToFetchDelay = 1
119    renameToDecodeDelay = 1
120    iewToDecodeDelay = 1
121    commitToDecodeDelay = 1
122    iewToRenameDelay = 1
123    commitToRenameDelay = 1
124    commitToIEWDelay = 1
125    fetchWidth = 3
126    fetchBufferSize = 16
127    fetchToDecodeDelay = 3
128    decodeWidth = 3
129    decodeToRenameDelay = 2
130    renameWidth = 3
131    renameToIEWDelay = 1
132    issueToExecuteDelay = 1
133    dispatchWidth = 6
134    issueWidth = 8
135    wbWidth = 8
136    fuPool = ex5_big_FUP()
137    iewToCommitDelay = 1
138    renameToROBDelay = 1
139    commitWidth = 8
140    squashWidth = 8
141    trapLatency = 13
142    backComSize = 5
143    forwardComSize = 5
144    numPhysIntRegs = 90
145    numPhysFloatRegs = 256
146    numIQEntries = 48
147    numROBEntries = 60
148
149    switched_out = False
150    branchPred = ex5_big_BP()
151
152class L1Cache(Cache):
153    tag_latency = 2
154    data_latency = 2
155    response_latency = 2
156    tgts_per_mshr = 8
157    # Consider the L2 a victim cache also for clean lines
158    writeback_clean = True
159
160# Instruction Cache
161class L1I(L1Cache):
162    mshrs = 2
163    size = '32kB'
164    assoc = 2
165    is_read_only = True
166
167# Data Cache
168class L1D(L1Cache):
169    mshrs = 6
170    size = '32kB'
171    assoc = 2
172    write_buffers = 16
173
174# TLB Cache
175# Use a cache as a L2 TLB
176class WalkCache(Cache):
177    tag_latency = 4
178    data_latency = 4
179    response_latency = 4
180    mshrs = 6
181    tgts_per_mshr = 8
182    size = '1kB'
183    assoc = 8
184    write_buffers = 16
185    is_read_only = True
186    # Writeback clean lines as well
187    writeback_clean = True
188
189# L2 Cache
190class L2(Cache):
191    tag_latency = 15
192    data_latency = 15
193    response_latency = 15
194    mshrs = 16
195    tgts_per_mshr = 8
196    size = '2MB'
197    assoc = 16
198    write_buffers = 8
199    prefetch_on_access = True
200    clusivity = 'mostly_excl'
201    # Simple stride prefetcher
202    prefetcher = StridePrefetcher(degree=8, latency = 1)
203    tags = BaseSetAssoc()
204    replacement_policy = RandomRP()
205