/gem5/src/gpu-compute/ |
H A D | cl_driver.hh | 56 int open(ThreadContext *tc, int mode, int flags); 57 int ioctl(ThreadContext *tc, unsigned req);
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/gem5/src/arch/arm/ |
H A D | interrupts.cc | 51 ArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type) const argument 55 bool highest_el_is_64 = ArmSystem::highestELIs64(tc); 57 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 60 hcr = tc->readMiscReg(MISCREG_HCR); 61 ExceptionLevel el = currEL(tc); 65 scr = tc->readMiscReg(MISCREG_SCR); 67 scr = tc->readMiscReg(MISCREG_SCR_EL3); 69 bool is_secure = inSecureState(tc);
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H A D | tlb.hh | 235 ThreadContext *tc, Mode mode, 240 ThreadContext *tc, Mode mode, 246 ThreadContext *tc); 247 bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, 320 * @param tc thread context to get the context id from 325 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 331 Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, 335 ThreadContext *tc, Mode mode) override 337 return translateFunctional(req, tc, mode, NormalTran); 354 Fault translateFs(const RequestPtr &req, ThreadContext *tc, Mod 468 getITBPtr(T *tc) argument 477 getDTBPtr(T *tc) argument [all...] |
H A D | process.cc | 110 ThreadContext * tc = system->getThreadContext(contextIds[i]); local 111 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR); 115 tc->setMiscReg(MISCREG_CPACR, cpacr); 117 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 119 tc->setMiscReg(MISCREG_FPEXC, fpexc); 129 ThreadContext * tc = system->getThreadContext(contextIds[i]); local 130 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 132 tc->setMiscReg(MISCREG_CPSR, cpsr); 133 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); 139 tc 211 ThreadContext *tc = system->getThreadContext(contextIds[0]); local 450 ThreadContext *tc = system->getThreadContext(contextIds[0]); local 483 getSyscallArg(ThreadContext *tc, int &i) argument 490 getSyscallArg(ThreadContext *tc, int &i) argument 497 getSyscallArg(ThreadContext *tc, int &i, int width) argument 516 getSyscallArg(ThreadContext *tc, int &i, int width) argument 523 setSyscallArg(ThreadContext *tc, int i, RegVal val) argument 530 setSyscallArg(ThreadContext *tc, int i, RegVal val) argument 537 setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) argument 554 setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) argument [all...] |
H A D | stage2_mmu.cc | 64 Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr, argument 73 fault = stage2Tlb()->translateFunctional(req, tc, BaseTLB::Read); 75 fault = stage2Tlb()->translateAtomic(req, tc, BaseTLB::Read); 101 Stage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr, argument 108 translation->translateTiming(tc); 122 ThreadContext *tc, BaseTLB::Mode mode) 137 tc->getCpuPtr()->clockPeriod(), req->getFlags()); 120 finish(const Fault &_fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) argument
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/gem5/src/base/ |
H A D | cp_annotate.cc | 150 CPA::getFrame(ThreadContext *tc) argument 154 return (tc->readMiscRegNoEffect(TheISA::IPR_PALtemp23) & 160 CPA::swSmBegin(ThreadContext *tc) argument 165 Arguments args(tc); 169 if (!TheISA::inUserMode(tc)) 171 tc->readIntReg(ReturnAddressReg), st, junk); 173 tc->getVirtProxy().readString(sm, args[0], 50); 174 System *sys = tc->getSystemPtr(); 188 uint64_t frame = getFrame(tc); 205 add(OP_LINK, FL_NONE, tc 252 swSmEnd(ThreadContext *tc) argument 320 swExplictBegin(ThreadContext *tc) argument 338 swAutoBegin(ThreadContext *tc, Addr next_pc) argument 392 swEnd(ThreadContext *tc) argument 423 swQ(ThreadContext *tc) argument 454 swDq(ThreadContext *tc) argument 483 swPq(ThreadContext *tc) argument 518 swRq(ThreadContext *tc) argument 549 swWf(ThreadContext *tc) argument 577 swWe(ThreadContext *tc) argument 605 swSq(ThreadContext *tc) argument 673 swAq(ThreadContext *tc) argument 710 swLink(ThreadContext *tc) argument 747 swIdentify(ThreadContext *tc) argument 765 swGetId(ThreadContext *tc) argument 785 swSyscallLink(ThreadContext *tc) argument [all...] |
/gem5/src/cpu/kvm/ |
H A D | x86_cpu.cc | 692 #define APPLY_IREG(kreg, mreg) regs.kreg = tc->readIntReg(mreg) 696 regs.rip = tc->instAddr() - tc->readMiscReg(MISCREG_CS_BASE); 704 regs.rflags = X86ISA::getRFlags(tc); 710 setKvmSegmentReg(ThreadContext *tc, struct kvm_segment &kvm_seg, argument 713 SegAttr attr(tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(index))); 715 kvm_seg.base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(index)); 716 kvm_seg.limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(index)); 717 kvm_seg.selector = tc->readMiscRegNoEffect(MISCREG_SEG_SEL(index)); 735 setKvmDTableReg(ThreadContext *tc, struc argument 824 updateKvmStateFPUCommon(ThreadContext *tc, T &fpu) argument 990 setContextSegment(ThreadContext *tc, const struct kvm_segment &kvm_seg, const int index) argument 1015 setContextSegment(ThreadContext *tc, const struct kvm_dtable &kvm_dtable, const int index) argument 1044 updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu) argument [all...] |
/gem5/src/arch/arm/kvm/ |
H A D | armv8_cpu.cc | 142 const uint64_t value(tc->readMiscReg(ri.idx)); 221 CPSR cpsr(tc->readMiscReg(MISCREG_CPSR)); 222 cpsr.nz = tc->readCCReg(CCREG_NZ); 223 cpsr.c = tc->readCCReg(CCREG_C); 224 cpsr.v = tc->readCCReg(CCREG_V); 226 cpsr.ge = tc->readCCReg(CCREG_GE); 234 const uint64_t value(tc->readMiscReg(ri.idx)); 240 const uint64_t value(tc->readIntReg(INTREG_X0 + i)); 246 const uint64_t value(tc->readIntReg(ri.idx)); 255 reg.s[j].i = tc [all...] |
/gem5/ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/ |
H A D | tlm_endian_conv.h | 229 tlm_endian_context *tc = txn->get_extension<tlm_endian_context>(); local 230 if(tc == 0) { 231 tc = global_tlm_endian_context_pool.pop(); 232 txn->set_extension(tc); 234 return tc; 344 tlm_endian_context *tc = txn->template get_extension<tlm_endian_context>(); local 346 txn->get_streaming_width(), tc->stream_width, sizeof_databus, tc->address, 347 tc->new_address, txn->get_data_length(), tc 357 tlm_endian_context *tc = establish_context(txn); local 534 tlm_endian_context *tc = txn->template get_extension<tlm_endian_context>(); local 564 tlm_endian_context *tc = establish_context(txn); local 673 tlm_endian_context *tc = txn->template get_extension<tlm_endian_context>(); local 700 tlm_endian_context *tc = establish_context(txn); local 763 tlm_endian_context *tc = establish_context(txn); local 779 tlm_endian_context *tc = txn->get_extension<tlm_endian_context>(); local [all...] |
/gem5/src/cpu/ |
H A D | profile.hh | 76 ProfileNode *consume(ThreadContext *tc, const StaticInstPtr &inst); 79 void dump(ThreadContext *tc, std::ostream &out) const; 84 FunctionProfile::consume(ThreadContext *tc, const StaticInstPtr &inst) argument 86 if (!trace.trace(tc, inst))
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H A D | inst_pb_trace.hh | 68 InstPBTraceRecord(InstPBTrace& _tracer, Tick when, ThreadContext *tc, argument 71 : InstRecord(when, tc, si, pc, mi), tracer(_tracer) 91 InstPBTraceRecord* getInstRecord(Tick when, ThreadContext *tc, const 121 * @param tc thread context for the cpu ID 125 void traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc);
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H A D | thread_context.cc | 166 serialize(const ThreadContext &tc, CheckpointOut &cp) argument 172 floatRegs[i] = tc.readFloatRegFlat(i); 179 vecRegs[i] = tc.readVecRegFlat(i); 185 vecPredRegs[i] = tc.readVecPredRegFlat(i); 191 intRegs[i] = tc.readIntRegFlat(i); 197 ccRegs[i] = tc.readCCRegFlat(i); 201 tc.pcState().serialize(cp); 207 unserialize(ThreadContext &tc, CheckpointIn &cp) argument 216 tc.setFloatRegFlat(i, floatRegs[i]); 221 tc [all...] |
/gem5/src/arch/alpha/ |
H A D | vtophys.hh | 48 Addr vtophys(ThreadContext *tc, Addr vaddr);
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/gem5/src/arch/power/ |
H A D | vtophys.hh | 47 Addr vtophys(ThreadContext *tc, Addr vaddr);
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/gem5/src/arch/sparc/ |
H A D | stacktrace.hh | 51 trace(ThreadContext *tc, const StaticInstPtr &inst) argument
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H A D | nativetrace.cc | 55 ThreadContext *tc = record->getThread(); local 65 regVal = tc->readIntReg(i); 71 SparcISA::PCState pc = tc->pcState(); 87 regVal = tc->readIntReg(SparcISA::NumIntArchRegs + 2);
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/gem5/src/sim/ |
H A D | arguments.cc | 55 return TheISA::getArgument(tc, number, size, fp);
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/gem5/src/arch/arm/linux/ |
H A D | system.hh | 95 * @param tc thread context that is currentyl executing */ 96 void mapPid(ThreadContext* tc, uint32_t pid); 134 virtual void process(ThreadContext* tc); 136 virtual void getTaskDetails(ThreadContext *tc, uint32_t &pid, 147 void getTaskDetails(ThreadContext *tc, uint32_t &pid, uint32_t &tgid,
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/gem5/src/arch/x86/ |
H A D | isa.hh | 57 ThreadContext *tc); 68 RegVal readMiscReg(int miscReg, ThreadContext *tc); 71 void setMiscReg(int miscReg, RegVal val, ThreadContext *tc); 140 void startup(ThreadContext *tc);
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H A D | process.hh | 85 void setSyscallReturn(ThreadContext *tc, 138 RegVal getSyscallArg(ThreadContext *tc, int &i) override; 141 void setSyscallArg(ThreadContext *tc, int i, RegVal val) override; 180 void syscall(int64_t callnum, ThreadContext *tc, 182 RegVal getSyscallArg(ThreadContext *tc, int &i) override; 183 RegVal getSyscallArg(ThreadContext *tc, int &i, int width) override; 184 void setSyscallArg(ThreadContext *tc, int i, RegVal val) override;
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H A D | tlb.hh | 109 Fault translateInt(const RequestPtr &req, ThreadContext *tc); 111 Fault translate(const RequestPtr &req, ThreadContext *tc, 126 const RequestPtr &req, ThreadContext *tc, Mode mode) override; 128 const RequestPtr &req, ThreadContext *tc, 140 * @param tc Thread context that created the request. 144 Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc,
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/gem5/src/arch/generic/ |
H A D | debugfaults.hh | 57 advancePC(ThreadContext *tc, const StaticInstPtr &inst) argument 60 auto pc = tc->pcState(); 62 tc->pcState(pc); 77 invoke(ThreadContext *tc, const StaticInstPtr &inst = 81 advancePC(tc, inst); 109 invoke(ThreadContext *tc, const StaticInstPtr &inst = 116 advancePC(tc, inst);
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/gem5/src/arch/mips/ |
H A D | tlb.hh | 116 const RequestPtr &req, ThreadContext *tc, Mode mode) override; 118 const RequestPtr &req, ThreadContext *tc, 122 ThreadContext *tc, Mode mode) const override; 125 Fault translateInst(const RequestPtr &req, ThreadContext *tc); 126 Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
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/gem5/src/arch/riscv/ |
H A D | tlb.hh | 115 const RequestPtr &req, ThreadContext *tc, Mode mode) override; 117 const RequestPtr &req, ThreadContext *tc, 121 ThreadContext *tc, Mode mode) const override; 124 Fault translateInst(const RequestPtr &req, ThreadContext *tc); 125 Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
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/gem5/src/arch/arm/insts/ |
H A D | misc64.cc | 87 MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg, argument 93 if (el <= EL1 && checkEL1Trap(tc, misc_reg, el)) { 100 if ((ArmSystem::haveVirtualization(tc) && el <= EL2) && 101 checkEL2Trap(tc, misc_reg, el, &is_vfp_neon)) { 109 if ((ArmSystem::haveSecurity(tc) && el <= EL3) && 110 checkEL3Trap(tc, misc_reg, el, &is_vfp_neon)) { 122 MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg, argument 125 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); 143 MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, argument 146 const CPTR cptr = tc 292 checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg, ExceptionLevel el, bool * is_vfp_neon) const argument 376 auto tc = xc->tcBase(); local [all...] |