arm/kvm/armv8_cpu.cc

142         const uint64_t value(tc->readMiscReg(ri.idx));
221     CPSR cpsr(tc->readMiscReg(MISCREG_CPSR));
222     cpsr.nz = tc->readCCReg(CCREG_NZ);
223     cpsr.c = tc->readCCReg(CCREG_C);
224     cpsr.v = tc->readCCReg(CCREG_V);
226         cpsr.ge = tc->readCCReg(CCREG_GE);
234         const uint64_t value(tc->readMiscReg(ri.idx));
240         const uint64_t value(tc->readIntReg(INTREG_X0 + i));
246         const uint64_t value(tc->readIntReg(ri.idx));
255             reg.s[j].i = tc->readFloatReg(reg_base + j);
268             value = tc->readMiscReg(ri.idx);
270             value = tc->readMiscReg(ri.idx);
277     setOneReg(INT_REG(regs.pc), tc->instAddr());
278     DPRINTF(KvmContext, "  PC := 0x%x\n", tc->instAddr());
289     tc->setMiscRegNoEffect(MISCREG_CPSR, cpsr);
290     tc->setCCReg(CCREG_NZ, cpsr.nz);
291     tc->setCCReg(CCREG_C, cpsr.c);
292     tc->setCCReg(CCREG_V, cpsr.v);
294         tc->setCCReg(CCREG_GE, cpsr.ge);
302         tc->setMiscRegNoEffect(ri.idx, value);
310         if (inAArch64(tc)) {
311             tc->setIntReg(INTREG_X0 + i, value);
313             tc->setIntRegFlat(IntReg64Map[INTREG_X0 + i], value);
320         tc->setIntReg(ri.idx, value);
329             tc->setFloatReg(reg_base + j, reg.s[j].i);
340             tc->setMiscReg(ri.idx, value);
342             tc->setMiscRegNoEffect(ri.idx, value);
347     pc.aarch64(inAArch64(tc));
349     pc.nextAArch64(inAArch64(tc));
355     tc->pcState(pc);