1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/sparc/nativetrace.hh"
32
33#include "arch/sparc/isa_traits.hh"
34#include "arch/sparc/registers.hh"
35#include "cpu/thread_context.hh"
36#include "params/SparcNativeTrace.hh"
37#include "sim/byteswap.hh"
38
39namespace Trace {
40
41static const char *intRegNames[SparcISA::NumIntArchRegs] = {
42    // Global registers
43    "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
44    // Output registers
45    "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
46    // Local registers
47    "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
48    // Input registers
49    "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
50};
51
52void
53Trace::SparcNativeTrace::check(NativeTraceRecord *record)
54{
55    ThreadContext *tc = record->getThread();
56
57    uint64_t regVal, realRegVal;
58
59    // Integer registers
60
61    // I doubt a real SPARC will describe more integer registers than this.
62    assert(SparcISA::NumIntArchRegs == 32);
63    const char **regName = intRegNames;
64    for (int i = 0; i < SparcISA::NumIntArchRegs; i++) {
65        regVal = tc->readIntReg(i);
66        read(&realRegVal, sizeof(realRegVal));
67        realRegVal = SparcISA::gtoh(realRegVal);
68        checkReg(*(regName++), regVal, realRegVal);
69    }
70
71    SparcISA::PCState pc = tc->pcState();
72    // PC
73    read(&realRegVal, sizeof(realRegVal));
74    realRegVal = SparcISA::gtoh(realRegVal);
75    regVal = pc.npc();
76    checkReg("pc", regVal, realRegVal);
77
78    // NPC
79    read(&realRegVal, sizeof(realRegVal));
80    realRegVal = SparcISA::gtoh(realRegVal);
81    pc.nnpc();
82    checkReg("npc", regVal, realRegVal);
83
84    // CCR
85    read(&realRegVal, sizeof(realRegVal));
86    realRegVal = SparcISA::gtoh(realRegVal);
87    regVal = tc->readIntReg(SparcISA::NumIntArchRegs + 2);
88    checkReg("ccr", regVal, realRegVal);
89}
90
91} // namespace Trace
92
93////////////////////////////////////////////////////////////////////////
94//
95//  ExeTracer Simulation Object
96//
97Trace::SparcNativeTrace *
98SparcNativeTraceParams::create()
99{
100    return new Trace::SparcNativeTrace(this);
101};
102