16019Shines@cs.fsu.edu/* 213882Sgiacomo.travaglini@arm.com * Copyright (c) 2010-2013, 2016, 2019 ARM Limited 37399SAli.Saidi@ARM.com * All rights reserved 47399SAli.Saidi@ARM.com * 57399SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67399SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77399SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87399SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97399SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107399SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117399SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127399SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137399SAli.Saidi@ARM.com * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 416019Shines@cs.fsu.edu */ 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TLB_HH__ 446019Shines@cs.fsu.edu#define __ARCH_ARM_TLB_HH__ 456019Shines@cs.fsu.edu 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#include "arch/arm/isa_traits.hh" 488229Snate@binkert.org#include "arch/arm/pagetable.hh" 496019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 506019Shines@cs.fsu.edu#include "arch/arm/vtophys.hh" 5110687SAndreas.Sandberg@ARM.com#include "arch/generic/tlb.hh" 526019Shines@cs.fsu.edu#include "base/statistics.hh" 536019Shines@cs.fsu.edu#include "mem/request.hh" 546116Snate@binkert.org#include "params/ArmTLB.hh" 5510463SAndreas.Sandberg@ARM.com#include "sim/probe/pmu.hh" 566019Shines@cs.fsu.edu 576019Shines@cs.fsu.educlass ThreadContext; 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edunamespace ArmISA { 606019Shines@cs.fsu.edu 617404SAli.Saidi@ARM.comclass TableWalker; 6210037SARM gem5 Developersclass Stage2LookUp; 6310037SARM gem5 Developersclass Stage2MMU; 6411395Sandreas.sandberg@arm.comclass TLB; 6511395Sandreas.sandberg@arm.com 6611395Sandreas.sandberg@arm.comclass TlbTestInterface 6711395Sandreas.sandberg@arm.com{ 6811395Sandreas.sandberg@arm.com public: 6911395Sandreas.sandberg@arm.com TlbTestInterface() {} 7011395Sandreas.sandberg@arm.com virtual ~TlbTestInterface() {} 7111395Sandreas.sandberg@arm.com 7211395Sandreas.sandberg@arm.com /** 7311395Sandreas.sandberg@arm.com * Check if a TLB translation should be forced to fail. 7411395Sandreas.sandberg@arm.com * 7511395Sandreas.sandberg@arm.com * @param req Request requiring a translation. 7611395Sandreas.sandberg@arm.com * @param is_priv Access from a privileged mode (i.e., not EL0) 7711395Sandreas.sandberg@arm.com * @param mode Access type 7811395Sandreas.sandberg@arm.com * @param domain Domain type 7911395Sandreas.sandberg@arm.com */ 8012749Sgiacomo.travaglini@arm.com virtual Fault translationCheck(const RequestPtr &req, bool is_priv, 8111395Sandreas.sandberg@arm.com BaseTLB::Mode mode, 8211395Sandreas.sandberg@arm.com TlbEntry::DomainType domain) = 0; 8311395Sandreas.sandberg@arm.com 8411395Sandreas.sandberg@arm.com /** 8511395Sandreas.sandberg@arm.com * Check if a page table walker access should be forced to fail. 8611395Sandreas.sandberg@arm.com * 8711395Sandreas.sandberg@arm.com * @param pa Physical address the walker is accessing 8811395Sandreas.sandberg@arm.com * @param size Walker access size 8911395Sandreas.sandberg@arm.com * @param va Virtual address that initiated the walk 9011395Sandreas.sandberg@arm.com * @param is_secure Access from secure state 9111395Sandreas.sandberg@arm.com * @param is_priv Access from a privileged mode (i.e., not EL0) 9211395Sandreas.sandberg@arm.com * @param mode Access type 9311395Sandreas.sandberg@arm.com * @param domain Domain type 9411395Sandreas.sandberg@arm.com * @param lookup_level Page table walker level 9511395Sandreas.sandberg@arm.com */ 9611395Sandreas.sandberg@arm.com virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure, 9711395Sandreas.sandberg@arm.com Addr is_priv, BaseTLB::Mode mode, 9811395Sandreas.sandberg@arm.com TlbEntry::DomainType domain, 9911395Sandreas.sandberg@arm.com LookupLevel lookup_level) = 0; 10011395Sandreas.sandberg@arm.com}; 1017404SAli.Saidi@ARM.com 1026019Shines@cs.fsu.educlass TLB : public BaseTLB 1036019Shines@cs.fsu.edu{ 1047294Sgblack@eecs.umich.edu public: 1057294Sgblack@eecs.umich.edu enum ArmFlags { 10610037SARM gem5 Developers AlignmentMask = 0x7, 1077294Sgblack@eecs.umich.edu 1087294Sgblack@eecs.umich.edu AlignByte = 0x0, 1097294Sgblack@eecs.umich.edu AlignHalfWord = 0x1, 11010037SARM gem5 Developers AlignWord = 0x2, 11110037SARM gem5 Developers AlignDoubleWord = 0x3, 11210037SARM gem5 Developers AlignQuadWord = 0x4, 11310037SARM gem5 Developers AlignOctWord = 0x5, 1147294Sgblack@eecs.umich.edu 11510037SARM gem5 Developers AllowUnaligned = 0x8, 1167404SAli.Saidi@ARM.com // Priv code operating as if it wasn't 11710037SARM gem5 Developers UserMode = 0x10, 1187294Sgblack@eecs.umich.edu // Because zero otherwise looks like a valid setting and may be used 1197294Sgblack@eecs.umich.edu // accidentally, this bit must be non-zero to show it was used on 1207294Sgblack@eecs.umich.edu // purpose. 12110037SARM gem5 Developers MustBeOne = 0x40 12210037SARM gem5 Developers }; 12310037SARM gem5 Developers 12410037SARM gem5 Developers enum ArmTranslationType { 12510037SARM gem5 Developers NormalTran = 0, 12610037SARM gem5 Developers S1CTran = 0x1, 12710037SARM gem5 Developers HypMode = 0x2, 12810037SARM gem5 Developers // Secure code operating as if it wasn't (required by some Address 12910037SARM gem5 Developers // Translate operations) 13011577SDylan.Johnson@ARM.com S1S2NsTran = 0x4, 13111577SDylan.Johnson@ARM.com // Address translation instructions (eg AT S1E0R_Xt) need to be handled 13211577SDylan.Johnson@ARM.com // in special ways during translation because they could need to act 13311577SDylan.Johnson@ARM.com // like a different EL than the current EL. The following flags are 13411577SDylan.Johnson@ARM.com // for these instructions 13511577SDylan.Johnson@ARM.com S1E0Tran = 0x8, 13611577SDylan.Johnson@ARM.com S1E1Tran = 0x10, 13711577SDylan.Johnson@ARM.com S1E2Tran = 0x20, 13811577SDylan.Johnson@ARM.com S1E3Tran = 0x40, 13911577SDylan.Johnson@ARM.com S12E0Tran = 0x80, 14011577SDylan.Johnson@ARM.com S12E1Tran = 0x100 1417294Sgblack@eecs.umich.edu }; 14212735Sandreas.sandberg@arm.com 14312735Sandreas.sandberg@arm.com /** 14412735Sandreas.sandberg@arm.com * Determine the EL to use for the purpose of a translation given 14512735Sandreas.sandberg@arm.com * a specific translation type. If the translation type doesn't 14612735Sandreas.sandberg@arm.com * specify an EL, we use the current EL. 14712735Sandreas.sandberg@arm.com */ 14812735Sandreas.sandberg@arm.com static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type); 14912735Sandreas.sandberg@arm.com 1506019Shines@cs.fsu.edu protected: 15110037SARM gem5 Developers TlbEntry* table; // the Page Table 15210037SARM gem5 Developers int size; // TLB Size 15310037SARM gem5 Developers bool isStage2; // Indicates this TLB is part of the second stage MMU 15410037SARM gem5 Developers bool stage2Req; // Indicates whether a stage 2 lookup is also required 15513374Sanouk.vanlaer@arm.com // Indicates whether a stage 2 lookup of the table descriptors is required. 15613374Sanouk.vanlaer@arm.com // Certain address translation instructions will intercept the IPA but the 15713374Sanouk.vanlaer@arm.com // table descriptors still need to be translated by the stage2. 15813374Sanouk.vanlaer@arm.com bool stage2DescReq; 15910037SARM gem5 Developers uint64_t _attr; // Memory attributes for last accessed TLB entry 16010037SARM gem5 Developers bool directToStage2; // Indicates whether all translation requests should 16110037SARM gem5 Developers // be routed directly to the stage 2 TLB 1627436Sdam.sunwoo@arm.com 1637404SAli.Saidi@ARM.com TableWalker *tableWalker; 16410037SARM gem5 Developers TLB *stage2Tlb; 16510037SARM gem5 Developers Stage2MMU *stage2Mmu; 1666019Shines@cs.fsu.edu 16711395Sandreas.sandberg@arm.com TlbTestInterface *test; 16811395Sandreas.sandberg@arm.com 1697399SAli.Saidi@ARM.com // Access Stats 1707734SAli.Saidi@ARM.com mutable Stats::Scalar instHits; 1717734SAli.Saidi@ARM.com mutable Stats::Scalar instMisses; 1727734SAli.Saidi@ARM.com mutable Stats::Scalar readHits; 1737734SAli.Saidi@ARM.com mutable Stats::Scalar readMisses; 1747734SAli.Saidi@ARM.com mutable Stats::Scalar writeHits; 1757734SAli.Saidi@ARM.com mutable Stats::Scalar writeMisses; 1767734SAli.Saidi@ARM.com mutable Stats::Scalar inserts; 1777734SAli.Saidi@ARM.com mutable Stats::Scalar flushTlb; 1787734SAli.Saidi@ARM.com mutable Stats::Scalar flushTlbMva; 1797734SAli.Saidi@ARM.com mutable Stats::Scalar flushTlbMvaAsid; 1807734SAli.Saidi@ARM.com mutable Stats::Scalar flushTlbAsid; 1817734SAli.Saidi@ARM.com mutable Stats::Scalar flushedEntries; 1827734SAli.Saidi@ARM.com mutable Stats::Scalar alignFaults; 1837734SAli.Saidi@ARM.com mutable Stats::Scalar prefetchFaults; 1847734SAli.Saidi@ARM.com mutable Stats::Scalar domainFaults; 1857734SAli.Saidi@ARM.com mutable Stats::Scalar permsFaults; 1867734SAli.Saidi@ARM.com 1877734SAli.Saidi@ARM.com Stats::Formula readAccesses; 1887734SAli.Saidi@ARM.com Stats::Formula writeAccesses; 1897734SAli.Saidi@ARM.com Stats::Formula instAccesses; 1906019Shines@cs.fsu.edu Stats::Formula hits; 1916019Shines@cs.fsu.edu Stats::Formula misses; 1926019Shines@cs.fsu.edu Stats::Formula accesses; 1936019Shines@cs.fsu.edu 19410463SAndreas.Sandberg@ARM.com /** PMU probe for TLB refills */ 19510463SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRefills; 19610463SAndreas.Sandberg@ARM.com 1977697SAli.Saidi@ARM.com int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 1987404SAli.Saidi@ARM.com 1996019Shines@cs.fsu.edu public: 20010037SARM gem5 Developers TLB(const ArmTLBParams *p); 20110037SARM gem5 Developers TLB(const Params *p, int _size, TableWalker *_walker); 2026019Shines@cs.fsu.edu 2039535Smrinmoy.ghosh@arm.com /** Lookup an entry in the TLB 2049535Smrinmoy.ghosh@arm.com * @param vpn virtual address 2059535Smrinmoy.ghosh@arm.com * @param asn context id/address space id to use 20610037SARM gem5 Developers * @param vmid The virtual machine ID used for stage 2 translation 20710037SARM gem5 Developers * @param secure if the lookup is secure 20810037SARM gem5 Developers * @param hyp if the lookup is done from hyp mode 2099535Smrinmoy.ghosh@arm.com * @param functional if the lookup should modify state 21010037SARM gem5 Developers * @param ignore_asn if on lookup asn should be ignored 21110037SARM gem5 Developers * @return pointer to TLB entry if it exists 2129535Smrinmoy.ghosh@arm.com */ 21310037SARM gem5 Developers TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 21410037SARM gem5 Developers bool secure, bool functional, 21514088Sgiacomo.travaglini@arm.com bool ignore_asn, ExceptionLevel target_el); 2169535Smrinmoy.ghosh@arm.com 2176019Shines@cs.fsu.edu virtual ~TLB(); 21810037SARM gem5 Developers 21911169Sandreas.hansson@arm.com void takeOverFrom(BaseTLB *otlb) override; 22010194SGeoffrey.Blake@arm.com 22110037SARM gem5 Developers /// setup all the back pointers 22211169Sandreas.hansson@arm.com void init() override; 22310037SARM gem5 Developers 22411395Sandreas.sandberg@arm.com void setTestInterface(SimObject *ti); 22511395Sandreas.sandberg@arm.com 22610717Sandreas.hansson@arm.com TableWalker *getTableWalker() { return tableWalker; } 22710717Sandreas.hansson@arm.com 22810717Sandreas.hansson@arm.com void setMMU(Stage2MMU *m, MasterID master_id); 22910037SARM gem5 Developers 2306019Shines@cs.fsu.edu int getsize() const { return size; } 2316019Shines@cs.fsu.edu 2327404SAli.Saidi@ARM.com void insert(Addr vaddr, TlbEntry &pte); 2337404SAli.Saidi@ARM.com 23412749Sgiacomo.travaglini@arm.com Fault getTE(TlbEntry **te, const RequestPtr &req, 23512749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode, 23610037SARM gem5 Developers Translation *translation, bool timing, bool functional, 23710037SARM gem5 Developers bool is_secure, ArmTranslationType tranType); 23810037SARM gem5 Developers 23912749Sgiacomo.travaglini@arm.com Fault getResultTe(TlbEntry **te, const RequestPtr &req, 24012749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode, 24112749Sgiacomo.travaglini@arm.com Translation *translation, bool timing, 24210037SARM gem5 Developers bool functional, TlbEntry *mergeTe); 24310037SARM gem5 Developers 24412749Sgiacomo.travaglini@arm.com Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode); 24512749Sgiacomo.travaglini@arm.com Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, 24610037SARM gem5 Developers ThreadContext *tc); 24714128Sgiacomo.travaglini@arm.com bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, 24814128Sgiacomo.travaglini@arm.com Mode mode); 24910037SARM gem5 Developers 25010037SARM gem5 Developers 25110037SARM gem5 Developers /** Reset the entire TLB 25210037SARM gem5 Developers * @param secure_lookup if the operation affects the secure world 25310037SARM gem5 Developers */ 25414088Sgiacomo.travaglini@arm.com void flushAllSecurity(bool secure_lookup, ExceptionLevel target_el, 25510037SARM gem5 Developers bool ignore_el = false); 25610037SARM gem5 Developers 25710037SARM gem5 Developers /** Remove all entries in the non secure world, depending on whether they 25810037SARM gem5 Developers * were allocated in hyp mode or not 25910037SARM gem5 Developers */ 26014088Sgiacomo.travaglini@arm.com void flushAllNs(ExceptionLevel target_el, bool ignore_el = false); 26110037SARM gem5 Developers 26210037SARM gem5 Developers 26310037SARM gem5 Developers /** Reset the entire TLB. Used for CPU switching to prevent stale 26410037SARM gem5 Developers * translations after multiple switches 26510037SARM gem5 Developers */ 26611169Sandreas.hansson@arm.com void flushAll() override 26710037SARM gem5 Developers { 26814088Sgiacomo.travaglini@arm.com flushAllSecurity(false, EL0, true); 26914088Sgiacomo.travaglini@arm.com flushAllSecurity(true, EL0, true); 27010037SARM gem5 Developers } 2717404SAli.Saidi@ARM.com 2727404SAli.Saidi@ARM.com /** Remove any entries that match both a va and asn 2737404SAli.Saidi@ARM.com * @param mva virtual address to flush 2747404SAli.Saidi@ARM.com * @param asn contextid/asn to flush on match 27510037SARM gem5 Developers * @param secure_lookup if the operation affects the secure world 2767404SAli.Saidi@ARM.com */ 27710037SARM gem5 Developers void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 27814088Sgiacomo.travaglini@arm.com ExceptionLevel target_el); 2797404SAli.Saidi@ARM.com 2807404SAli.Saidi@ARM.com /** Remove any entries that match the asn 2817404SAli.Saidi@ARM.com * @param asn contextid/asn to flush on match 28210037SARM gem5 Developers * @param secure_lookup if the operation affects the secure world 2837404SAli.Saidi@ARM.com */ 28414088Sgiacomo.travaglini@arm.com void flushAsid(uint64_t asn, bool secure_lookup, 28514088Sgiacomo.travaglini@arm.com ExceptionLevel target_el); 2867404SAli.Saidi@ARM.com 2877404SAli.Saidi@ARM.com /** Remove all entries that match the va regardless of asn 2887404SAli.Saidi@ARM.com * @param mva address to flush from cache 28910037SARM gem5 Developers * @param secure_lookup if the operation affects the secure world 2907404SAli.Saidi@ARM.com */ 29114088Sgiacomo.travaglini@arm.com void flushMva(Addr mva, bool secure_lookup, ExceptionLevel target_el); 2927404SAli.Saidi@ARM.com 29311584SDylan.Johnson@ARM.com /** 29411584SDylan.Johnson@ARM.com * Invalidate all entries in the stage 2 TLB that match the given ipa 29511584SDylan.Johnson@ARM.com * and the current VMID 29611584SDylan.Johnson@ARM.com * @param ipa the address to invalidate 29711584SDylan.Johnson@ARM.com * @param secure_lookup if the operation affects the secure world 29811584SDylan.Johnson@ARM.com */ 29914088Sgiacomo.travaglini@arm.com void flushIpaVmid(Addr ipa, bool secure_lookup, ExceptionLevel target_el); 30011584SDylan.Johnson@ARM.com 30112749Sgiacomo.travaglini@arm.com Fault trickBoxCheck(const RequestPtr &req, Mode mode, 30212749Sgiacomo.travaglini@arm.com TlbEntry::DomainType domain); 30312749Sgiacomo.travaglini@arm.com 30412749Sgiacomo.travaglini@arm.com Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, 30512749Sgiacomo.travaglini@arm.com bool is_exec, bool is_write, 30612749Sgiacomo.travaglini@arm.com TlbEntry::DomainType domain, 30712749Sgiacomo.travaglini@arm.com LookupLevel lookup_level); 30811584SDylan.Johnson@ARM.com 30910037SARM gem5 Developers void printTlb() const; 3107404SAli.Saidi@ARM.com 31111169Sandreas.hansson@arm.com void demapPage(Addr vaddr, uint64_t asn) override 3126019Shines@cs.fsu.edu { 31310037SARM gem5 Developers // needed for x86 only 31410037SARM gem5 Developers panic("demapPage() is not implemented.\n"); 3156019Shines@cs.fsu.edu } 3166019Shines@cs.fsu.edu 3177694SAli.Saidi@ARM.com /** 3187694SAli.Saidi@ARM.com * Do a functional lookup on the TLB (for debugging) 3197694SAli.Saidi@ARM.com * and don't modify any internal state 3207694SAli.Saidi@ARM.com * @param tc thread context to get the context id from 3217694SAli.Saidi@ARM.com * @param vaddr virtual address to translate 3227694SAli.Saidi@ARM.com * @param pa returned physical address 3237694SAli.Saidi@ARM.com * @return if the translation was successful 3247694SAli.Saidi@ARM.com */ 3257694SAli.Saidi@ARM.com bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 3267694SAli.Saidi@ARM.com 3278733Sgeoffrey.blake@arm.com /** 3288733Sgeoffrey.blake@arm.com * Do a functional lookup on the TLB (for checker cpu) that 3298733Sgeoffrey.blake@arm.com * behaves like a normal lookup without modifying any page table state. 3308733Sgeoffrey.blake@arm.com */ 33112749Sgiacomo.travaglini@arm.com Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, 33212749Sgiacomo.travaglini@arm.com Mode mode, ArmTranslationType tranType); 33312419Sgabeblack@google.com Fault 33412749Sgiacomo.travaglini@arm.com translateFunctional(const RequestPtr &req, 33512749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode) override 33612419Sgabeblack@google.com { 33712419Sgabeblack@google.com return translateFunctional(req, tc, mode, NormalTran); 33812419Sgabeblack@google.com } 3398733Sgeoffrey.blake@arm.com 3407436Sdam.sunwoo@arm.com /** Accessor functions for memory attributes for last accessed TLB entry 3417436Sdam.sunwoo@arm.com */ 3427436Sdam.sunwoo@arm.com void 34310037SARM gem5 Developers setAttr(uint64_t attr) 3447436Sdam.sunwoo@arm.com { 3457436Sdam.sunwoo@arm.com _attr = attr; 3467436Sdam.sunwoo@arm.com } 34710037SARM gem5 Developers 34810037SARM gem5 Developers uint64_t 3497436Sdam.sunwoo@arm.com getAttr() const 3507436Sdam.sunwoo@arm.com { 3517436Sdam.sunwoo@arm.com return _attr; 3527436Sdam.sunwoo@arm.com } 3537436Sdam.sunwoo@arm.com 35412749Sgiacomo.travaglini@arm.com Fault translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, 3558733Sgeoffrey.blake@arm.com Translation *translation, bool &delay, 35610037SARM gem5 Developers bool timing, ArmTranslationType tranType, bool functional = false); 35712749Sgiacomo.travaglini@arm.com Fault translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, 3587404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing); 35912749Sgiacomo.travaglini@arm.com Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, 36012406Sgabeblack@google.com ArmTranslationType tranType); 36112406Sgabeblack@google.com Fault 36212749Sgiacomo.travaglini@arm.com translateAtomic(const RequestPtr &req, 36312749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode) override 36412406Sgabeblack@google.com { 36512406Sgabeblack@google.com return translateAtomic(req, tc, mode, NormalTran); 36612406Sgabeblack@google.com } 36712406Sgabeblack@google.com void translateTiming( 36812749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, 36910037SARM gem5 Developers Translation *translation, Mode mode, 37012406Sgabeblack@google.com ArmTranslationType tranType); 37112406Sgabeblack@google.com void 37212749Sgiacomo.travaglini@arm.com translateTiming(const RequestPtr &req, ThreadContext *tc, 37312406Sgabeblack@google.com Translation *translation, Mode mode) override 37412406Sgabeblack@google.com { 37512406Sgabeblack@google.com translateTiming(req, tc, translation, mode, NormalTran); 37612406Sgabeblack@google.com } 37712749Sgiacomo.travaglini@arm.com Fault translateComplete(const RequestPtr &req, ThreadContext *tc, 37810037SARM gem5 Developers Translation *translation, Mode mode, ArmTranslationType tranType, 37910037SARM gem5 Developers bool callFromS2); 38012406Sgabeblack@google.com Fault finalizePhysical( 38112749Sgiacomo.travaglini@arm.com const RequestPtr &req, 38212749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode) const override; 3836116Snate@binkert.org 38411168Sandreas.hansson@arm.com void drainResume() override; 3859439SAndreas.Sandberg@ARM.com 3866019Shines@cs.fsu.edu // Checkpointing 38711168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 38811168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 3896019Shines@cs.fsu.edu 39011169Sandreas.hansson@arm.com void regStats() override; 3917749SAli.Saidi@ARM.com 39211168Sandreas.hansson@arm.com void regProbePoints() override; 39310463SAndreas.Sandberg@ARM.com 3948922Swilliam.wang@arm.com /** 39513784Sgabeblack@google.com * Get the table walker port. This is used for migrating 3968922Swilliam.wang@arm.com * port connections during a CPU takeOverFrom() call. For 3978922Swilliam.wang@arm.com * architectures that do not have a table walker, NULL is 3988922Swilliam.wang@arm.com * returned, hence the use of a pointer rather than a 3998922Swilliam.wang@arm.com * reference. For ARM this method will always return a valid port 4008922Swilliam.wang@arm.com * pointer. 4018922Swilliam.wang@arm.com * 4028922Swilliam.wang@arm.com * @return A pointer to the walker master port 4038922Swilliam.wang@arm.com */ 40413784Sgabeblack@google.com Port *getTableWalkerPort() override; 4057781SAli.Saidi@ARM.com 4067749SAli.Saidi@ARM.com // Caching misc register values here. 4077749SAli.Saidi@ARM.com // Writing to misc registers needs to invalidate them. 4087749SAli.Saidi@ARM.com // translateFunctional/translateSe/translateFs checks if they are 4097749SAli.Saidi@ARM.com // invalid and call updateMiscReg if necessary. 4107749SAli.Saidi@ARM.comprotected: 41110854SNathanael.Premillieu@arm.com CPSR cpsr; 41210037SARM gem5 Developers bool aarch64; 41310037SARM gem5 Developers ExceptionLevel aarch64EL; 4147749SAli.Saidi@ARM.com SCTLR sctlr; 41510037SARM gem5 Developers SCR scr; 4167749SAli.Saidi@ARM.com bool isPriv; 41710037SARM gem5 Developers bool isSecure; 41810037SARM gem5 Developers bool isHyp; 41910037SARM gem5 Developers TTBCR ttbcr; 42010037SARM gem5 Developers uint16_t asid; 42110037SARM gem5 Developers uint8_t vmid; 4227749SAli.Saidi@ARM.com PRRR prrr; 4237749SAli.Saidi@ARM.com NMRR nmrr; 42410037SARM gem5 Developers HCR hcr; 4257749SAli.Saidi@ARM.com uint32_t dacr; 4267749SAli.Saidi@ARM.com bool miscRegValid; 42711152Smitch.hayenga@arm.com ContextID miscRegContext; 42810037SARM gem5 Developers ArmTranslationType curTranType; 42910037SARM gem5 Developers 43010037SARM gem5 Developers // Cached copies of system-level properties 43110037SARM gem5 Developers bool haveLPAE; 43210037SARM gem5 Developers bool haveVirtualization; 43310037SARM gem5 Developers bool haveLargeAsid64; 43410037SARM gem5 Developers 43512005Sandreas.sandberg@arm.com AddrRange m5opRange; 43612005Sandreas.sandberg@arm.com 43710037SARM gem5 Developers void updateMiscReg(ThreadContext *tc, 43810037SARM gem5 Developers ArmTranslationType tranType = NormalTran); 43910037SARM gem5 Developers 4407749SAli.Saidi@ARM.compublic: 4418299Schander.sudanthi@arm.com const Params * 4428299Schander.sudanthi@arm.com params() const 4438299Schander.sudanthi@arm.com { 4448299Schander.sudanthi@arm.com return dynamic_cast<const Params *>(_params); 4458299Schander.sudanthi@arm.com } 4467749SAli.Saidi@ARM.com inline void invalidateMiscReg() { miscRegValid = false; } 44710037SARM gem5 Developers 44810037SARM gem5 Developersprivate: 44910037SARM gem5 Developers /** Remove any entries that match both a va and asn 45010037SARM gem5 Developers * @param mva virtual address to flush 45110037SARM gem5 Developers * @param asn contextid/asn to flush on match 45210037SARM gem5 Developers * @param secure_lookup if the operation affects the secure world 45310037SARM gem5 Developers * @param ignore_asn if the flush should ignore the asn 45410037SARM gem5 Developers */ 45510037SARM gem5 Developers void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 45614088Sgiacomo.travaglini@arm.com bool ignore_asn, ExceptionLevel target_el); 45711395Sandreas.sandberg@arm.com 45811395Sandreas.sandberg@arm.com public: /* Testing */ 45912749Sgiacomo.travaglini@arm.com Fault testTranslation(const RequestPtr &req, Mode mode, 46011395Sandreas.sandberg@arm.com TlbEntry::DomainType domain); 46111395Sandreas.sandberg@arm.com Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, 46211395Sandreas.sandberg@arm.com TlbEntry::DomainType domain, 46311395Sandreas.sandberg@arm.com LookupLevel lookup_level); 4646019Shines@cs.fsu.edu}; 4656019Shines@cs.fsu.edu 46612605Sgiacomo.travaglini@arm.comtemplate<typename T> 46712605Sgiacomo.travaglini@arm.comTLB * 46812605Sgiacomo.travaglini@arm.comgetITBPtr(T *tc) 46912605Sgiacomo.travaglini@arm.com{ 47012605Sgiacomo.travaglini@arm.com auto tlb = static_cast<TLB *>(tc->getITBPtr()); 47112605Sgiacomo.travaglini@arm.com assert(tlb); 47212605Sgiacomo.travaglini@arm.com return tlb; 47312605Sgiacomo.travaglini@arm.com} 47412605Sgiacomo.travaglini@arm.com 47512605Sgiacomo.travaglini@arm.comtemplate<typename T> 47612605Sgiacomo.travaglini@arm.comTLB * 47712605Sgiacomo.travaglini@arm.comgetDTBPtr(T *tc) 47812605Sgiacomo.travaglini@arm.com{ 47912605Sgiacomo.travaglini@arm.com auto tlb = static_cast<TLB *>(tc->getDTBPtr()); 48012605Sgiacomo.travaglini@arm.com assert(tlb); 48112605Sgiacomo.travaglini@arm.com return tlb; 48212605Sgiacomo.travaglini@arm.com} 48312605Sgiacomo.travaglini@arm.com 4847811Ssteve.reinhardt@amd.com} // namespace ArmISA 4856019Shines@cs.fsu.edu 4866019Shines@cs.fsu.edu#endif // __ARCH_ARM_TLB_HH__ 487