1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 *          Steve Reinhardt
31 *          Jaidev Patwardhan
32 *          Korey Sewell
33 */
34
35#ifndef __ARCH_MIPS_TLB_HH__
36#define __ARCH_MIPS_TLB_HH__
37
38#include <map>
39
40#include "arch/generic/tlb.hh"
41#include "arch/mips/isa_traits.hh"
42#include "arch/mips/pagetable.hh"
43#include "arch/mips/utility.hh"
44#include "arch/mips/vtophys.hh"
45#include "base/statistics.hh"
46#include "mem/request.hh"
47#include "params/MipsTLB.hh"
48#include "sim/sim_object.hh"
49
50class ThreadContext;
51
52/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
53   However, to maintain compatibility with other architectures, we'll
54   simply create an ITLB and DTLB that will point to the real TLB */
55namespace MipsISA {
56
57class TLB : public BaseTLB
58{
59  protected:
60    typedef std::multimap<Addr, int> PageTable;
61    PageTable lookupTable;      // Quick lookup into page table
62
63    MipsISA::PTE *table;        // the Page Table
64    int size;                   // TLB Size
65    int nlu;                    // not last used entry (for replacement)
66
67    void nextnlu() { if (++nlu >= size) nlu = 0; }
68    MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
69
70    mutable Stats::Scalar read_hits;
71    mutable Stats::Scalar read_misses;
72    mutable Stats::Scalar read_acv;
73    mutable Stats::Scalar read_accesses;
74    mutable Stats::Scalar write_hits;
75    mutable Stats::Scalar write_misses;
76    mutable Stats::Scalar write_acv;
77    mutable Stats::Scalar write_accesses;
78    Stats::Formula hits;
79    Stats::Formula misses;
80    Stats::Formula accesses;
81
82  public:
83    typedef MipsTLBParams Params;
84    TLB(const Params *p);
85
86    int probeEntry(Addr vpn,uint8_t) const;
87    MipsISA::PTE *getEntry(unsigned) const;
88    virtual ~TLB();
89
90    void takeOverFrom(BaseTLB *otlb) override {}
91
92    int smallPages;
93    int getsize() const { return size; }
94
95    MipsISA::PTE &index(bool advance = true);
96    void insert(Addr vaddr, MipsISA::PTE &pte);
97    void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
98    void flushAll() override;
99    void demapPage(Addr vaddr, uint64_t asn) override
100    {
101        panic("demapPage unimplemented.\n");
102    }
103
104    // static helper functions... really
105    static bool validVirtualAddress(Addr vaddr);
106
107    static Fault checkCacheability(const RequestPtr &req);
108
109    // Checkpointing
110    void serialize(CheckpointOut &cp) const override;
111    void unserialize(CheckpointIn &cp) override;
112
113    void regStats() override;
114
115    Fault translateAtomic(
116            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
117    void translateTiming(
118            const RequestPtr &req, ThreadContext *tc,
119            Translation *translation, Mode mode) override;
120    Fault finalizePhysical(
121            const RequestPtr &req,
122            ThreadContext *tc, Mode mode) const override;
123
124  private:
125    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
126    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
127};
128
129}
130
131
132
133#endif // __MIPS_MEMORY_HH__
134