arm/insts/misc64.cc

87 MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg,
93     if (el <= EL1 && checkEL1Trap(tc, misc_reg, el)) {
100     if ((ArmSystem::haveVirtualization(tc) && el <= EL2) &&
101         checkEL2Trap(tc, misc_reg, el, &is_vfp_neon)) {
109     if ((ArmSystem::haveSecurity(tc) && el <= EL3) &&
110         checkEL3Trap(tc, misc_reg, el, &is_vfp_neon)) {
122 MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
125     const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
143 MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
146     const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2);
147     const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
148     const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
149     const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
276             if (tc->getIsaPtr()->haveGICv3CpuIfc())
281             if (tc->getIsaPtr()->haveGICv3CpuIfc())
292 MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
295     const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL3);
376     auto tc = xc->tcBase();
377     const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
380     Fault fault = trap(tc, miscReg, el, imm);