Searched refs:slave (Results 51 - 75 of 92) sorted by relevance

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/gem5/tests/configs/
H A Dgpu-randomtest-ruby.py122 tester.cpuInstDataPort = ruby_port.slave
124 tester.cpuDataPort = ruby_port.slave
126 tester.cpuInstPort = ruby_port.slave
H A Do3-timing-mp-ruby.py58 system.system_port = system.membus.slave
H A Dsimple-atomic-mp-ruby.py56 system.system_port = system.membus.slave
/gem5/configs/ruby/
H A DGPU_VIPER_Baseline.py420 dir_cntrl.requestFromCores.slave = ruby_system.network.master
423 dir_cntrl.responseFromCores.slave = ruby_system.network.master
426 dir_cntrl.unblockFromCores.slave = ruby_system.network.master
429 dir_cntrl.probeToCore.master = ruby_system.network.slave
432 dir_cntrl.responseToCore.master = ruby_system.network.slave
456 cp_cntrl.requestFromCore.master = ruby_system.network.slave
459 cp_cntrl.responseFromCore.master = ruby_system.network.slave
462 cp_cntrl.unblockFromCore.master = ruby_system.network.slave
465 cp_cntrl.probeToCore.slave = ruby_system.network.master
468 cp_cntrl.responseToCore.slave
[all...]
H A DMOESI_AMD_Base.py266 dir_cntrl.requestFromCores.slave = ruby_system.network.master
269 dir_cntrl.responseFromCores.slave = ruby_system.network.master
272 dir_cntrl.unblockFromCores.slave = ruby_system.network.master
275 dir_cntrl.probeToCore.master = ruby_system.network.slave
278 dir_cntrl.responseToCore.master = ruby_system.network.slave
310 cp_cntrl.requestFromCore.master = ruby_system.network.slave
313 cp_cntrl.responseFromCore.master = ruby_system.network.slave
316 cp_cntrl.unblockFromCore.master = ruby_system.network.slave
319 cp_cntrl.probeToCore.slave = ruby_system.network.master
322 cp_cntrl.responseToCore.slave
[all...]
H A DRuby.py114 dir_cntrl.memory = crossbar.slave
199 sys_port_proxy.pio_master_port = piobus.slave
206 system.system_port = system.sys_port_proxy.slave
213 cpu_seq.pio_master_port = piobus.slave
214 cpu_seq.mem_master_port = piobus.slave
H A DAMD_Base_Constructor.py124 cp_cntrl.requestFromCore = ruby_system.network.slave
125 cp_cntrl.responseFromCore = ruby_system.network.slave
126 cp_cntrl.unblockFromCore = ruby_system.network.slave
/gem5/src/dev/arm/
H A DSMMUv3.py49 slave = SlavePort('Device port') variable in class:SMMUv3SlaveInterface
51 ats_slave = SlavePort('ATS slave port')
196 self.master = bus.slave
202 slave_interface.slave = device.master
204 slave_interface.slave = device.dma
/gem5/configs/example/
H A Dfs.py161 test_sys.iobus.master = test_sys.ruby._io_port.slave
171 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
172 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
175 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
176 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
180 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
188 test_sys.iocache.mem_side = test_sys.membus.slave
191 test_sys.iobridge.slave = test_sys.iobus.master
192 test_sys.iobridge.master = test_sys.membus.slave
286 drive_sys.iobridge.slave
[all...]
H A Dse.py264 system.cpu[i].icache_port = ruby_port.slave
265 system.cpu[i].dcache_port = ruby_port.slave
268 system.cpu[i].interrupts[0].int_master = ruby_port.slave
270 system.cpu[i].itb.walker.port = ruby_port.slave
271 system.cpu[i].dtb.walker.port = ruby_port.slave
275 system.system_port = system.membus.slave
H A Dapu_se.py272 compute_units[-1].ldsPort = compute_units[-1].ldsBus.slave
459 system.cpu[i].icache_port = ruby_port.slave
460 system.cpu[i].dcache_port = ruby_port.slave
462 ruby_port.mem_master_port = system.piobus.slave
465 system.cpu[i].interrupts[0].int_master = system.piobus.slave
468 system.cpu[i].itb.walker.port = ruby_port.slave
469 system.cpu[i].dtb.walker.port = ruby_port.slave
488 system.ruby._cpu_ports[gpu_port_idx].slave[j]
496 system.ruby._cpu_ports[gpu_port_idx].slave
503 system.ruby._cpu_ports[gpu_port_idx + i * 2].slave
[all...]
H A Druby_gpu_random_test.py158 tester.cpuInstDataPort = ruby_port.slave
160 tester.cpuDataPort = ruby_port.slave
162 tester.cpuInstPort = ruby_port.slave
H A Dmemtest.py281 cache.mem_side = xbar.slave
285 cache.mem_side = xbar.slave
297 tester.port = xbar.slave
327 root.system.system_port = last_subsys.xbar.slave
/gem5/configs/learning_gem5/part1/
H A Dcaches.py67 self.mem_side = bus.slave
136 self.mem_side = bus.slave
H A Dtwo_level.py130 system.cpu.interrupts[0].int_master = system.membus.slave
134 system.system_port = system.membus.slave
/gem5/configs/common/
H A DFSConfig.py116 self.bridge.master = self.iobus.slave
117 self.bridge.slave = self.membus.master
119 self.tsunami.ide.dma = self.iobus.slave
120 self.tsunami.ethernet.dma = self.iobus.slave
122 self.system_port = self.membus.slave
167 self.bridge.master = self.iobus.slave
168 self.bridge.slave = self.membus.master
203 self.system_port = self.membus.slave
227 self.bridge.master = self.iobus.slave
230 self.bridge.slave
[all...]
/gem5/configs/dram/
H A Dlat_mem_rd.py261 system.tgen.port = system.monitor.slave
285 system.l1cache.mem_side = system.l2cache.xbar.slave
292 system.l2cache.mem_side = system.l3cache.xbar.slave
294 system.l3cache.mem_side = system.membus.slave
297 system.system_port = system.membus.slave
H A Dsweep.py171 system.tgen.port = system.monitor.slave
172 system.monitor.master = system.membus.slave
175 system.system_port = system.membus.slave
H A Dlow_power_sweep.py229 system.tgen.port = system.monitor.slave
230 system.monitor.master = system.membus.slave
233 system.system_port = system.membus.slave
/gem5/src/dev/x86/
H A DSouthBridge.py98 self.pic1.slave = self.pic2
106 self.ide.dma = bus.slave
113 self.io_apic.int_master = bus.slave
/gem5/src/dev/storage/
H A Dide_ctrl.hh96 IdeDisk *master, *slave; member in struct:IdeController::Channel
107 selected = selectBit ? slave : master;
/gem5/src/cpu/testers/traffic_gen/
H A DBaseTrafficGen.py117 exec('self.%s = bus.slave' % p)
119 self.port = bus.slave
/gem5/src/mem/
H A DCommMonitor.py54 slave = SlavePort("Slave port") variable in class:CommMonitor
H A DXBar.py54 slave = VectorSlavePort("Vector port for connecting masters") variable in class:BaseXBar
78 # a default slave port
79 default = MasterPort("Port for connecting an optional default slave")
/gem5/src/mem/ruby/system/
H A DSequencer.py40 slave = VectorSlavePort("CPU slave port") variable in class:RubyPort
44 pio_slave_port = SlavePort("Ruby pio slave port")

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