112598Snikos.nikoleris@arm.com# Copyright (c) 2012, 2017-2018 ARM Limited 28706Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88706Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128706Sandreas.hansson@arm.com# 136892SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 146892SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 156892SBrad.Beckmann@amd.com# All rights reserved. 166892SBrad.Beckmann@amd.com# 176892SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 186892SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 196892SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 206892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 216892SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 226892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 236892SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 246892SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 256892SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 266892SBrad.Beckmann@amd.com# this software without specific prior written permission. 276892SBrad.Beckmann@amd.com# 286892SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296892SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306892SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316892SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326892SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336892SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346892SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356892SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366892SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376892SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386892SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396892SBrad.Beckmann@amd.com# 406892SBrad.Beckmann@amd.com# Authors: Brad Beckmann 416892SBrad.Beckmann@amd.com 4212564Sgabeblack@google.comfrom __future__ import print_function 4312564Sgabeblack@google.com 447563SBrad.Beckmann@amd.comimport math 456892SBrad.Beckmann@amd.comimport m5 466892SBrad.Beckmann@amd.comfrom m5.objects import * 476892SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 4810118Snilay@cs.wisc.edufrom m5.util import addToPath, fatal 4910118Snilay@cs.wisc.edu 5013400Sodanrc@yahoo.com.braddToPath('../') 5113400Sodanrc@yahoo.com.br 5211682Sandreas.hansson@arm.comfrom common import MemConfig 5313885Sdavid.hashe@amd.comfrom common import FileSystemConfig 5411662Stushar@ece.gatech.edu 5511670Sandreas.hansson@arm.comfrom topologies import * 5611670Sandreas.hansson@arm.comfrom network import Network 576892SBrad.Beckmann@amd.com 587538SBrad.Beckmann@amd.comdef define_options(parser): 598939SBrad.Beckmann@amd.com # By default, ruby uses the simple timing cpu 6012014Sgabeblack@google.com parser.set_defaults(cpu_type="TimingSimpleCPU") 618939SBrad.Beckmann@amd.com 629791Sakash.bagdia@arm.com parser.add_option("--ruby-clock", action="store", type="string", 639791Sakash.bagdia@arm.com default='2GHz', 649791Sakash.bagdia@arm.com help="Clock for blocks running at Ruby system's speed") 659791Sakash.bagdia@arm.com 6610525Snilay@cs.wisc.edu parser.add_option("--access-backing-store", action="store_true", default=False, 6710525Snilay@cs.wisc.edu help="Should ruby maintain a second copy of memory") 6810525Snilay@cs.wisc.edu 699841Snilay@cs.wisc.edu # Options related to cache structure 709841Snilay@cs.wisc.edu parser.add_option("--ports", action="store", type="int", default=4, 719841Snilay@cs.wisc.edu help="used of transitions per cycle which is a proxy \ 729841Snilay@cs.wisc.edu for the number of ports.") 739841Snilay@cs.wisc.edu 7411662Stushar@ece.gatech.edu # network options are in network/Network.py 757538SBrad.Beckmann@amd.com 767538SBrad.Beckmann@amd.com # ruby mapping options 777917SBrad.Beckmann@amd.com parser.add_option("--numa-high-bit", type="int", default=0, 787563SBrad.Beckmann@amd.com help="high order address bit to use for numa mapping. " \ 797563SBrad.Beckmann@amd.com "0 = highest bit, not specified = lowest bit") 807538SBrad.Beckmann@amd.com 817566SBrad.Beckmann@amd.com parser.add_option("--recycle-latency", type="int", default=10, 827566SBrad.Beckmann@amd.com help="Recycle latency for ruby controller input buffers") 837809Snilay@cs.wisc.edu 847538SBrad.Beckmann@amd.com protocol = buildEnv['PROTOCOL'] 8513774Sandreas.sandberg@arm.com exec("from . import %s" % protocol) 867538SBrad.Beckmann@amd.com eval("%s.define_options(parser)" % protocol) 8711670Sandreas.hansson@arm.com Network.define_options(parser) 887538SBrad.Beckmann@amd.com 8910524Snilay@cs.wisc.edudef setup_memory_controllers(system, ruby, dir_cntrls, options): 9010524Snilay@cs.wisc.edu ruby.block_size_bytes = options.cacheline_size 9110524Snilay@cs.wisc.edu ruby.memory_size_bits = 48 9210524Snilay@cs.wisc.edu 9310524Snilay@cs.wisc.edu index = 0 9410524Snilay@cs.wisc.edu mem_ctrls = [] 9510524Snilay@cs.wisc.edu crossbars = [] 9610524Snilay@cs.wisc.edu 9712976Snikos.nikoleris@arm.com if options.numa_high_bit: 9812976Snikos.nikoleris@arm.com dir_bits = int(math.log(options.num_dirs, 2)) 9912976Snikos.nikoleris@arm.com intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1) 10012976Snikos.nikoleris@arm.com else: 10112976Snikos.nikoleris@arm.com # if the numa_bit is not specified, set the directory bits as the 10212976Snikos.nikoleris@arm.com # lowest bits above the block offset bits 10312976Snikos.nikoleris@arm.com intlv_size = options.cacheline_size 10412976Snikos.nikoleris@arm.com 10510524Snilay@cs.wisc.edu # Sets bits to be used for interleaving. Creates memory controllers 10610524Snilay@cs.wisc.edu # attached to a directory controller. A separate controller is created 10710524Snilay@cs.wisc.edu # for each address range as the abstract memory can handle only one 10810524Snilay@cs.wisc.edu # contiguous address range as of now. 10910524Snilay@cs.wisc.edu for dir_cntrl in dir_cntrls: 11010524Snilay@cs.wisc.edu crossbar = None 11110524Snilay@cs.wisc.edu if len(system.mem_ranges) > 1: 11210720Sandreas.hansson@arm.com crossbar = IOXBar() 11310524Snilay@cs.wisc.edu crossbars.append(crossbar) 11410524Snilay@cs.wisc.edu dir_cntrl.memory = crossbar.slave 11510524Snilay@cs.wisc.edu 11612976Snikos.nikoleris@arm.com dir_ranges = [] 11710524Snilay@cs.wisc.edu for r in system.mem_ranges: 11810524Snilay@cs.wisc.edu mem_ctrl = MemConfig.create_mem_ctrl( 11910524Snilay@cs.wisc.edu MemConfig.get(options.mem_type), r, index, options.num_dirs, 12012976Snikos.nikoleris@arm.com int(math.log(options.num_dirs, 2)), intlv_size) 12110524Snilay@cs.wisc.edu 12211616Sdavid.j.hashe@gmail.com if options.access_backing_store: 12311616Sdavid.j.hashe@gmail.com mem_ctrl.kvm_map=False 12411616Sdavid.j.hashe@gmail.com 12510524Snilay@cs.wisc.edu mem_ctrls.append(mem_ctrl) 12612976Snikos.nikoleris@arm.com dir_ranges.append(mem_ctrl.range) 12710524Snilay@cs.wisc.edu 12810524Snilay@cs.wisc.edu if crossbar != None: 12910524Snilay@cs.wisc.edu mem_ctrl.port = crossbar.master 13010524Snilay@cs.wisc.edu else: 13110524Snilay@cs.wisc.edu mem_ctrl.port = dir_cntrl.memory 13210524Snilay@cs.wisc.edu 13314038Smatthew.poremba@amd.com # Enable low-power DRAM states if option is set 13414038Smatthew.poremba@amd.com if issubclass(MemConfig.get(options.mem_type), DRAMCtrl): 13514038Smatthew.poremba@amd.com mem_ctrl.enable_dram_powerdown = \ 13614038Smatthew.poremba@amd.com options.enable_dram_powerdown 13714038Smatthew.poremba@amd.com 13810524Snilay@cs.wisc.edu index += 1 13912976Snikos.nikoleris@arm.com dir_cntrl.addr_ranges = dir_ranges 14010524Snilay@cs.wisc.edu 14110524Snilay@cs.wisc.edu system.mem_ctrls = mem_ctrls 14210524Snilay@cs.wisc.edu 14310524Snilay@cs.wisc.edu if len(crossbars) > 0: 14410524Snilay@cs.wisc.edu ruby.crossbars = crossbars 14510524Snilay@cs.wisc.edu 14610524Snilay@cs.wisc.edu 1479100SBrad.Beckmann@amd.comdef create_topology(controllers, options): 1489100SBrad.Beckmann@amd.com """ Called from create_system in configs/ruby/<protocol>.py 1499100SBrad.Beckmann@amd.com Must return an object which is a subclass of BaseTopology 1509100SBrad.Beckmann@amd.com found in configs/topologies/BaseTopology.py 1519100SBrad.Beckmann@amd.com This is a wrapper for the legacy topologies. 1529100SBrad.Beckmann@amd.com """ 15313774Sandreas.sandberg@arm.com exec("import topologies.%s as Topo" % options.topology) 1549100SBrad.Beckmann@amd.com topology = eval("Topo.%s(controllers)" % options.topology) 1559100SBrad.Beckmann@amd.com return topology 1569100SBrad.Beckmann@amd.com 15712598Snikos.nikoleris@arm.comdef create_system(options, full_system, system, piobus = None, dma_ports = [], 15812598Snikos.nikoleris@arm.com bootmem=None): 1596892SBrad.Beckmann@amd.com 16010524Snilay@cs.wisc.edu system.ruby = RubySystem() 1618436SBrad.Beckmann@amd.com ruby = system.ruby 1628436SBrad.Beckmann@amd.com 16313885Sdavid.hashe@amd.com # Generate pseudo filesystem 16413980Sjason@lowepower.com FileSystemConfig.config_filesystem(system, options) 16513885Sdavid.hashe@amd.com 16611662Stushar@ece.gatech.edu # Create the network object 16711662Stushar@ece.gatech.edu (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \ 16811662Stushar@ece.gatech.edu Network.create_network(options, ruby) 16910311Snilay@cs.wisc.edu ruby.network = network 17010311Snilay@cs.wisc.edu 17110551Ssteve.reinhardt@amd.com protocol = buildEnv['PROTOCOL'] 17213774Sandreas.sandberg@arm.com exec("from . import %s" % protocol) 17310311Snilay@cs.wisc.edu try: 17410311Snilay@cs.wisc.edu (cpu_sequencers, dir_cntrls, topology) = \ 17510551Ssteve.reinhardt@amd.com eval("%s.create_system(options, full_system, system, dma_ports,\ 17612598Snikos.nikoleris@arm.com bootmem, ruby)" 17710551Ssteve.reinhardt@amd.com % protocol) 17810311Snilay@cs.wisc.edu except: 17912564Sgabeblack@google.com print("Error: could not create sytem for ruby protocol %s" % protocol) 18010311Snilay@cs.wisc.edu raise 18110311Snilay@cs.wisc.edu 18211662Stushar@ece.gatech.edu # Create the network topology 18311662Stushar@ece.gatech.edu topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 18411662Stushar@ece.gatech.edu RouterClass) 18511662Stushar@ece.gatech.edu 18613885Sdavid.hashe@amd.com # Register the topology elements with faux filesystem (SE mode only) 18713885Sdavid.hashe@amd.com if not full_system: 18813885Sdavid.hashe@amd.com topology.registerTopology(options) 18913885Sdavid.hashe@amd.com 19013885Sdavid.hashe@amd.com 19111662Stushar@ece.gatech.edu # Initialize network based on topology 19211662Stushar@ece.gatech.edu Network.init_network(options, network, InterfaceClass) 19311662Stushar@ece.gatech.edu 19410311Snilay@cs.wisc.edu # Create a port proxy for connecting the system port. This is 19510311Snilay@cs.wisc.edu # independent of the protocol and kept in the protocol-agnostic 19610311Snilay@cs.wisc.edu # part (i.e. here). 19710311Snilay@cs.wisc.edu sys_port_proxy = RubyPortProxy(ruby_system = ruby) 19811596Sandreas.sandberg@arm.com if piobus is not None: 19911596Sandreas.sandberg@arm.com sys_port_proxy.pio_master_port = piobus.slave 20010311Snilay@cs.wisc.edu 20110311Snilay@cs.wisc.edu # Give the system port proxy a SimObject parent without creating a 20210311Snilay@cs.wisc.edu # full-fledged controller 20310311Snilay@cs.wisc.edu system.sys_port_proxy = sys_port_proxy 20410311Snilay@cs.wisc.edu 20510311Snilay@cs.wisc.edu # Connect the system port for loading of binaries etc 20610311Snilay@cs.wisc.edu system.system_port = system.sys_port_proxy.slave 2079148Spowerjg@cs.wisc.edu 20810524Snilay@cs.wisc.edu setup_memory_controllers(system, ruby, dir_cntrls, options) 20910116Snilay@cs.wisc.edu 21010116Snilay@cs.wisc.edu # Connect the cpu sequencers and the piobus 21110116Snilay@cs.wisc.edu if piobus != None: 21210116Snilay@cs.wisc.edu for cpu_seq in cpu_sequencers: 21310116Snilay@cs.wisc.edu cpu_seq.pio_master_port = piobus.slave 21410116Snilay@cs.wisc.edu cpu_seq.mem_master_port = piobus.slave 21510116Snilay@cs.wisc.edu 21610116Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "x86": 21710116Snilay@cs.wisc.edu cpu_seq.pio_slave_port = piobus.master 21810116Snilay@cs.wisc.edu 21911172Snilay@cs.wisc.edu ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks 22010120Snilay@cs.wisc.edu ruby._cpu_ports = cpu_sequencers 22110012Snilay@cs.wisc.edu ruby.num_of_sequencers = len(cpu_sequencers) 22210525Snilay@cs.wisc.edu 22310630Snilay@cs.wisc.edu # Create a backing copy of physical memory in case required 22410630Snilay@cs.wisc.edu if options.access_backing_store: 22510706Spower.jg@gmail.com ruby.access_backing_store = True 22610706Spower.jg@gmail.com ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 22710630Snilay@cs.wisc.edu in_addr_map=False) 22810630Snilay@cs.wisc.edu 22912976Snikos.nikoleris@arm.comdef create_directories(options, bootmem, ruby_system, system): 23012065Snikos.nikoleris@arm.com dir_cntrl_nodes = [] 23113731Sandreas.sandberg@arm.com for i in range(options.num_dirs): 23212065Snikos.nikoleris@arm.com dir_cntrl = Directory_Controller() 23312065Snikos.nikoleris@arm.com dir_cntrl.version = i 23412065Snikos.nikoleris@arm.com dir_cntrl.directory = RubyDirectoryMemory() 23512065Snikos.nikoleris@arm.com dir_cntrl.ruby_system = ruby_system 23612065Snikos.nikoleris@arm.com 23712065Snikos.nikoleris@arm.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 23812065Snikos.nikoleris@arm.com dir_cntrl_nodes.append(dir_cntrl) 23912598Snikos.nikoleris@arm.com 24012598Snikos.nikoleris@arm.com if bootmem is not None: 24112598Snikos.nikoleris@arm.com rom_dir_cntrl = Directory_Controller() 24212598Snikos.nikoleris@arm.com rom_dir_cntrl.directory = RubyDirectoryMemory() 24312598Snikos.nikoleris@arm.com rom_dir_cntrl.ruby_system = ruby_system 24412598Snikos.nikoleris@arm.com rom_dir_cntrl.version = i + 1 24512598Snikos.nikoleris@arm.com rom_dir_cntrl.memory = bootmem.port 24612598Snikos.nikoleris@arm.com rom_dir_cntrl.addr_ranges = bootmem.range 24712598Snikos.nikoleris@arm.com return (dir_cntrl_nodes, rom_dir_cntrl) 24812598Snikos.nikoleris@arm.com 24912598Snikos.nikoleris@arm.com return (dir_cntrl_nodes, None) 25012065Snikos.nikoleris@arm.com 25110529Smorr@cs.wisc.edudef send_evicts(options): 25210529Smorr@cs.wisc.edu # currently, 2 scenarios warrant forwarding evictions to the CPU: 25310529Smorr@cs.wisc.edu # 1. The O3 model must keep the LSQ coherent with the caches 25410529Smorr@cs.wisc.edu # 2. The x86 mwait instruction is built on top of coherence invalidations 25512066Snikos.nikoleris@arm.com # 3. The local exclusive monitor in ARM systems 25612066Snikos.nikoleris@arm.com if options.cpu_type == "DerivO3CPU" or \ 25712066Snikos.nikoleris@arm.com buildEnv['TARGET_ISA'] in ('x86', 'arm'): 25810529Smorr@cs.wisc.edu return True 25910529Smorr@cs.wisc.edu return False 260