Searched refs:delay (Results 51 - 75 of 143) sorted by relevance

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/gem5/util/tlm/src/
H A Dsc_master_port.cc146 tlm::tlm_phase& phase, sc_core::sc_time& delay)
165 peq.notify(trans, phase, delay);
249 auto delay = sc_core::SC_ZERO_TIME; local
251 auto status = transactor->socket->nb_transport_bw(trans, phase, delay);
281 auto delay = local
285 t += delay;
338 auto delay = sc_core::sc_time::from_value(pkt->payloadDelay); local
361 sendBeginResp(trans, delay);
369 sc_core::sc_time& delay)
375 auto status = transactor->socket->nb_transport_bw(trans, phase, delay);
145 nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) argument
368 sendBeginResp(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) argument
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/gem5/src/arch/sparc/
H A Dua2005.cc334 int delay; local
335 delay = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
337 assert(delay >= 0 && "stick compare missed interrupt cycle");
339 if (delay == 0 || tc->status() == ThreadContext::Suspended) {
346 cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(delay)));
358 int delay; local
362 delay = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
364 assert(delay >= 0 && "hstick compare missed interrupt cycle");
366 if (delay == 0 || tc->status() == ThreadContext::Suspended) {
374 cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(delay)));
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/gem5/ext/mcpat/cacti/
H A Dnuca.cc42 #define LATCH_DELAY 28e-12 /* latch delay in s (later should use FO4 TODO) */
107 //TODO: convert latch delay to FO4 */
260 /* find delay, area, and power for wires */
266 calc_cycles(wire_horizontal[wr]->delay,
270 calc_cycles(wire_vertical[wr]->delay,
315 curr_acclat = 2 * avg_lat + 2 * (router_s[ro]->delay *
334 wire_horizontal[wr]->delay) * flit_width +
336 wire_horizontal[wr]->delay);
359 /* network delay/power */
363 /* bank delay/powe
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H A Ddecoder.h66 double delay; member in class:Decoder
213 // returns <delay, risetime>
232 double delay; member in class:Driver
/gem5/src/mem/
H A Dbridge.cc63 delay(_delay), ranges(_ranges.begin(), _ranges.end()),
74 delay(_delay), reqQueueLimit(_req_limit),
82 ticksToCycles(p->delay), p->resp_size, p->ranges),
84 ticksToCycles(p->delay), p->req_size)
133 // technically the packet only reaches us after the header delay,
139 slavePort.schedTimingResp(pkt, bridge.clockEdge(delay) +
187 // delay, and typically we also need to deserialise any
193 masterPort.schedTimingReq(pkt, bridge.clockEdge(delay) +
346 return delay * bridge.clockPeriod() + masterPort.sendAtomic(pkt);
H A Dserial_link.cc66 masterPort(_masterPort), delay(_delay),
79 slavePort(_slavePort), delay(_delay), reqQueueLimit(_req_limit),
87 ticksToCycles(p->delay), p->resp_size, p->ranges),
89 ticksToCycles(p->delay), p->req_size),
149 Cycles cycles = delay;
210 Cycles cycles = delay;
378 return delay * serial_link.clockPeriod() + masterPort.sendAtomic(pkt);
H A Dmem_delay.cc59 fatal("Memory delay is not connected on both sides.\n");
112 const Tick delay = parent.delaySnoopResp(pkt); local
114 return delay + parent.slavePort.sendAtomicSnoop(pkt);
133 const Tick delay = parent.delayReq(pkt) + parent.delayResp(pkt); local
135 return delay + parent.masterPort.sendAtomic(pkt);
H A Dbridge.hh64 * responses. The bridge has a fixed delay for packets passing through
71 * the bridge will delay accepting the packet until space becomes
116 /** Minimum request delay though this bridge. */
117 const Cycles delay; member in class:Bridge::BridgeSlavePort
124 * queue for a specified delay to model the processing delay
170 * @param _delay the delay in cycles from receiving to sending
182 * @param pkt a response to send out after a delay
236 /** Minimum delay though this bridge. */
237 const Cycles delay; member in class:Bridge::BridgeMasterPort
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H A Dserial_link.hh112 /** Minimum request delay though this serial_link. */
113 const Cycles delay; member in class:SerialLink::SerialLinkSlavePort
120 * queue for a specified delay to model the processing delay
161 * @param _delay the delay in cycles from receiving to sending
174 * @param pkt a response to send out after a delay
228 /** Minimum delay though this serial_link. */
229 const Cycles delay; member in class:SerialLink::SerialLinkMasterPort
233 * queue for a specified delay to model the processing delay
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/gem5/util/tlm/examples/master_port/
H A Dtraffic_generator.hh74 sc_core::sc_time& delay);
/gem5/src/cpu/testers/traffic_gen/
H A Dtrace_gen.hh182 Tick nextPacketTick(bool elastic, Tick delay) const;
H A Dtrace_gen.cc96 TraceGen::nextPacketTick(bool elastic, Tick delay) const
111 // if the playback is supposed to be elastic, add the delay
113 tickOffset += delay;
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ui/
H A Djal.S36 # Test delay slot instructions not executed nor bypassed
/gem5/src/dev/storage/
H A DIde.py38 delay = Param.Latency('1us', "Fixed disk delay in microseconds") variable in class:IdeDisk
/gem5/src/dev/arm/
H A Dsmmu_v3_cmdexec.cc52 a.delay = 0;
/gem5/src/mem/ruby/network/garnet2.0/
H A Dflit.hh69 void set_src_delay(Cycles delay) { src_delay = delay; } argument
/gem5/src/systemc/tests/systemc/compliance_1666/test203b/
H A Dtest203b.cpp44 void proc(int delay) argument
46 wait(delay * sc_time(1, SC_NS));
/gem5/src/gpu-compute/
H A Dmisc.hh66 void preset(uint32_t delay) argument
68 lookAheadAvail = std::max(lookAheadAvail, delay + (*tcnt) - numStages);
/gem5/src/mem/cache/
H A Dmshr_queue.cc88 MSHRQueue::delay(MSHR *mshr, Tick delay_ticks) function in class:MSHRQueue
90 mshr->delay(delay_ticks);
/gem5/util/m5/
H A Dlua_gem5Op.c125 uint64_t delay = lua_tointeger(L, 1); local
127 m5_checkpoint(delay, period);
143 uint64_t delay = lua_tointeger(L, 1); local
145 m5_dump_stats(delay, period);
152 uint64_t delay = lua_tointeger(L, 1); local
154 m5_dump_reset_stats(delay, period);
/gem5/src/systemc/tlm_bridge/
H A Dtlm_to_gem5.cc110 auto delay = sc_core::SC_ZERO_TIME; local
112 auto status = socket->nb_transport_bw(trans, phase, delay);
120 sc_core::sc_time &delay)
126 auto status = socket->nb_transport_bw(trans, phase, delay);
242 sc_core::sc_time &delay)
260 peq.notify(trans, phase, delay);
292 auto delay = local
296 t += delay;
398 auto delay = sc_core::sc_time::from_value(pkt->payloadDelay); local
421 sendBeginResp(trans, delay);
119 sendBeginResp(tlm::tlm_generic_payload &trans, sc_core::sc_time &delay) argument
240 nb_transport_fw( tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_core::sc_time &delay) argument
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/gem5/src/dev/net/
H A Detherswitch.cc51 p->output_buffer_size, p->delay,
129 uint64_t outputBufferSize, Tick delay,
131 : EtherInt(name), ticksPerByte(rate), switchDelay(delay),
205 Tick delay = (Tick)ceil(((double)outputFifo.front()->simLength local
208 delay += random_mt.random<Tick>(0, delayVar);
209 delay += switchDelay;
210 return delay;
127 Interface(const std::string &name, EtherSwitch *etherSwitch, uint64_t outputBufferSize, Tick delay, Tick delay_var, double rate, unsigned id) argument
/gem5/src/systemc/tests/tlm/update_original/
H A Dupdate_original.cpp65 sc_time delay = SC_ZERO_TIME; local
127 socket->b_transport( *trans, delay ); // Blocking transport call
169 virtual void b_transport( tlm::tlm_generic_payload& trans, sc_time& delay )
178 init_socket->b_transport( trans2, delay );
203 virtual void b_transport( tlm::tlm_generic_payload& trans, sc_time& delay )
/gem5/src/systemc/core/
H A Dscheduler.hh233 delayed(const ::sc_core::sc_time &delay) argument
235 return getCurTick() + delay.value();
240 schedule(ScEvent *event, const ::sc_core::sc_time &delay) argument
242 Tick tick = delayed(delay);
247 if (delay.value() == 0) {
/gem5/src/systemc/tests/systemc/kernel/phase_callbacks/test05/
H A Dsimulation_callbacks.cpp86 static const sc_time delay(1, SC_NS);
176 timed_ev.notify(delay);

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